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    SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE
    21.
    发明申请
    SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE 有权
    用于存储器件的自适应位速率编程的系统和方法

    公开(公告)号：US20140215124A1

    公开(公告)日：2014-07-31

    申请号：US13751883

    申请日：2013-01-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Wolf Allers ,  Jan Otterstedt ,  Mihail Jefremow ,  Edvin Paparisto ,  Leonardo Castro

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3486

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

    Abstract translation: 本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。 根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择 用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

    Operation Scheme for Non-Volatile Memory
    22.
    发明申请
    Operation Scheme for Non-Volatile Memory 有权
    非易失性存储器的操作方案

    公开(公告)号：US20140153348A1

    公开(公告)日：2014-06-05

    申请号：US13690299

    申请日：2012-11-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Thomas Nirschl ,  Jan Otterstedt ,  Alexander Duch

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C16/0425 ,  G11C16/3427 ,  G11C16/349

    Abstract: A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted.

    Abstract translation: 操作集成电路的方法包括确定至少一个存储器单元的至少一个特性并对至少一个存储器单元进行操作，其中基于所确定的至少一个特征来确定至少一个附加存储器单元的干扰 调整。

    Apparatus and Method for Producing a Bit Sequence
    23.
    发明申请
    Apparatus and Method for Producing a Bit Sequence 审中-公开
    用于产生位序列的装置和方法

    公开(公告)号：US20130094648A1

    公开(公告)日：2013-04-18

    申请号：US13648634

    申请日：2012-10-10

    Applicant: Infineon Technologies AG

    Inventor： Rainer Goettfert ,  Berndt Gammel ,  Jan Otterstedt

    IPC: H04L9/28

    CPC classification number: H04L9/28 ,  H04L9/0643 ,  H04L9/0866 ,  H04L2209/34

    Abstract: A method for reconstructing a physically unclonable function (PUF) A for use in an electronic appliance is provided. The method includes producing a checksum C, producing a defective PUF B and reconstructing the PUF A from the defective PUF B using an error correction algorithm. The algorithm produces a plurality of ambiguous results (A1, A2, . . . , An) for the PUF A in a fraction of the cases and a single result, which may be incorrect, in all other cases. The method also includes determining by means of the checksum C which of the plurality of ambiguous results (A1, A2, . . . , An) is the correct PUF A or of whether a single result corresponds to the correct PUF A.

    Abstract translation: 提供了一种用于重建用于电子设备的物理不可克隆功能（PUF）A的方法。 该方法包括产生校验和C，产生缺陷PUF B，并使用纠错算法从缺陷PUF B重构PUF A. 在所有其他情况下，该算法在一小部分情况下为PUF A产生多个模糊结果（A1，A2，...，An）和单个结果，这可能是不正确的。 该方法还包括通过校验和C来确定多个模糊结果（A1，A2，...，An）中的哪一个是正确的PUF A或单个结果是否对应于正确的PUF A.

    Apparatus and methods for detecting a property from electromagnetic radiation sensor data
    24.
    发明授权
    Apparatus and methods for detecting a property from electromagnetic radiation sensor data 有权

    公开(公告)号：US11620507B2

    公开(公告)日：2023-04-04

    申请号：US15983736

    申请日：2018-05-18

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt

    IPC: G06N3/08 ,  G02F1/21 ,  G06V10/143 ,  G06V10/145 ,  G06V40/10 ,  G06N3/04 ,  G06V40/20 ,  G06V40/16 ,  G06F3/01

    Abstract: An apparatus includes a sensor module. The sensor module includes an electromagnetic radiation sensor configured to provide electromagnetic radiation sensor data. The sensor module further includes a coded mask configured to modulate electromagnetic radiation incident to the electromagnetic radiation sensor and from which the electromagnetic radiation sensor data is generated. The apparatus further includes a computation module configured to obtain the electromagnetic radiation sensor data from the electromagnetic radiation sensor. The computation module is further configured to detect a property from the electromagnetic radiation sensor data using an artificial neural network. The computation module is further configured to output information related to the detected property via an output.

    Device and method for generating error correction information
    25.
    发明授权
    Device and method for generating error correction information 有权

    公开(公告)号：US11231990B2

    公开(公告)日：2022-01-25

    申请号：US16688240

    申请日：2019-11-19

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt

    IPC: G06F11/10 ,  G06F11/07

    Abstract: A device comprises an electronic data memory and a control unit configured to store a bit sequence in the electronic data memory as a stored bit sequence. The control unit is configured to check the stored bit sequence for bit errors, to generate error correction information having information about a correct bit value in the stored bit sequence, and to store the error correction information.

    Digital address compensation for memory devices
    27.
    发明授权
    Digital address compensation for memory devices 有权

    公开(公告)号：US11062761B1

    公开(公告)日：2021-07-13

    申请号：US16740893

    申请日：2020-01-13

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Wolf Allers ,  Christian Peters

    IPC: G11C11/4094 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097

    Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.

    CHIP AND METHOD FOR DETECTING AN ATTACK ON A CHIP
    29.
    发明申请
    CHIP AND METHOD FOR DETECTING AN ATTACK ON A CHIP 有权
    用于检测芯片上的攻击的芯片和方法

    公开(公告)号：US20150143550A1

    公开(公告)日：2015-05-21

    申请号：US14080847

    申请日：2013-11-15

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Thomas Kuenemund

    IPC: G06F21/70 ,  G06F21/86

    CPC classification number: G06F21/87

    Abstract: According to one embodiment, a chip is described comprising a substrate; an energy source configured to provide energy to the substrate; an energy receiver configured to receive energy from the energy source via the substrate and a determiner configured to determine a value of a parameter of the energy transmission between the energy source and the energy receiver, to check whether the value matches a predetermined value of the parameter and to output a signal depending on the result of the check.

    Abstract translation: 根据一个实施例，描述了包括衬底的芯片; 能量源，被配置为向所述衬底提供能量; 能量接收器，被配置为经由衬底从能量源接收能量;以及确定器，被配置为确定能量源和能量接收器之间的能量传输的参数的值，以检查该值是否匹配参数的预定值 并根据检查结果输出信号。

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