公开(公告)号：US10325803B2

公开(公告)日：2019-06-18

申请号：US15969868

申请日：2018-05-03

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Gerhard Schmidt ,  Martin Sporn ,  Markus Kahn ,  Juergen Steinbrenner ,  Ravi Joshi

IPC: C23C14/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/16 ,  H01L29/06 ,  H01L29/40 ,  C23C14/58 ,  C23C14/34 ,  C23C14/35 ,  H01L29/73

Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

公开(公告)号：US10106398B2

公开(公告)日：2018-10-23

申请号：US14724224

申请日：2015-05-28

Applicant: Infineon Technologies AG

Inventor： Ulrich Schmid ,  Tobias Frischmuth ,  Peter Irsigler ,  Thomas Grille ,  Daniel Maurer ,  Ursula Hedenig ,  Markus Kahn ,  Guenter Denifl ,  Michael Schneider

IPC: B81C1/00 ,  B81B3/00

Abstract: A micromechanical structure comprises a substrate and a functional structure arranged at the substrate. The functional structure comprises a functional region which is deflectable with respect to the substrate responsive to a force acting on the functional region. The functional structure comprises a carbon layer arrangement, wherein a basis material of the carbon layer arrangement is a carbon material.

公开(公告)号：US20180076036A1

公开(公告)日：2018-03-15

申请号：US15582940

申请日：2017-05-01

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/16 ,  H01L21/324 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/7802

Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

公开(公告)号：US20180002167A1

公开(公告)日：2018-01-04

申请号：US15636702

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Tobias Frischmuth ,  Guenter Denifl ,  Thomas Grille ,  Ursula Hedenig ,  Markus Kahn ,  Daniel Maurer ,  Ulrich Schmid ,  Michael Schneider

IPC: B81C1/00 ,  H04R19/04 ,  G01Q60/24 ,  H04R19/02 ,  B81B3/00 ,  G01L1/00

Abstract: A micromechanical structure in accordance with various embodiments may include: a substrate; and a functional structure arranged at the substrate; wherein the functional structure includes a functional region which is deflectable with respect to the substrate responsive to a force acting on the functional region; and wherein at least a section of the functional region has an elastic modulus in the range from about 5 GPa to about 70 GPa.

公开(公告)号：US09741618B2

公开(公告)日：2017-08-22

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09728480B2

公开(公告)日：2017-08-08

申请号：US14699704

申请日：2015-04-29

Applicant: Infineon Technologies AG

Inventor： Kurt Matoy ,  Hubert Maier ,  Christian Krenn ,  Elfriede Kraxner Wellenzohn ,  Helmut Schoenherr ,  Juergen Steinbrenner ,  Markus Kahn ,  Silvana Fister ,  Christoph Brunner ,  Herbert Gietler ,  Uwe Hoeckele

IPC: H01L21/3105 ,  H01L23/31 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3171 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/76801 ,  H01L23/291

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

公开(公告)号：US20150348824A1

公开(公告)日：2015-12-03

申请号：US14291107

申请日：2014-05-30

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Gerhard Schmidt ,  Martin Sporn ,  Markus Kahn ,  Juergen Steinbrenner ,  Ravi Joshi

IPC: H01L21/762 ,  H01L29/40 ,  C23C14/06 ,  C23C14/35 ,  C23C14/58 ,  H01L29/06 ,  C23C14/34

CPC classification number: H01L21/762 ,  C23C14/0605 ,  C23C14/345 ,  C23C14/35 ,  C23C14/5806 ,  H01L21/02527 ,  H01L21/02631 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/408 ,  H01L29/73

Abstract: According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.

Abstract translation: 根据各种实施例，半导体晶片可以包括：包括集成电路结构的半导体本体; 以及至少一个四面体无定形碳层，形成在所述集成电路结构中的至少一个或所述集成电路结构中的至少一个，所述至少一个四面体非晶碳层可以包括大于约0.4的sp3-杂化碳的物质量分数和大于约0.4的物质量分数 的氢小于约0.1。

公开(公告)号：US20140235035A1

公开(公告)日：2014-08-21

申请号：US14260903

申请日：2014-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底中形成开口。 该方法包括在开口内形成虚拟填充材料并使衬底变薄以暴露虚拟填充材料。 去除虚拟填充材料。

公开(公告)号：US11804415B2

公开(公告)日：2023-10-31

申请号：US17333107

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Markus Kahn ,  Oliver Humbel ,  Philipp Sebastian Koch ,  Angelika Koprowski ,  Christian Maier ,  Gerhard Schmidt ,  Juergen Steinbrenner

IPC: H01L29/06 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  C23C16/34 ,  H01L21/02

CPC classification number: H01L23/3171 ,  C23C16/345 ,  H01L21/0217 ,  H01L21/02271 ,  H01L23/291 ,  H01L23/564 ,  H01L29/0623

Abstract: A semiconductor device includes: a semiconductor body having an active region and an edge termination region between the active region and a side surface of the semiconductor body; a first portion including silicon and nitrogen; a second portion including silicon and nitrogen, the second portion being in direct contact with the first portion; and a front side metallization in contact with the semiconductor body in the active region. The first portion separates the second portion from the semiconductor body. An average silicon content in the first portion is higher than in the second portion. The front side metallization is interposed between the first portion and the semiconductor body in the active region but not in the edge termination region, and/or the first portion and the second portion are both present in the edge termination region but not in the active region.

公开(公告)号：US20230343726A1

公开(公告)日：2023-10-26

申请号：US18215467

申请日：2023-06-28

Applicant: Infineon Technologies AG

Inventor： Angelika Koprowski ,  Oliver Humbel ,  Markus Kahn ,  Carsten Schaeffer

IPC: H01L23/00 ,  H01L29/40

CPC classification number: H01L23/564 ,  H01L29/402

Abstract: A high voltage semiconductor device includes a semiconductor substrate including an upper surface, a high voltage electrically conductive structure disposed on the semiconductor substrate, a first step topography at an edge of the high voltage electrically conductive structure, a varying lateral doping zone disposed within the semiconductor substrate, and a layer stack including an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer, and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer, wherein the layer stack conforms to the first step topography and extends over the varying lateral doping zone.