公开(公告)号：US20150177373A1

公开(公告)日：2015-06-25

申请号：US14135069

申请日：2013-12-19

Applicant: Infineon Technologies AG

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Walter Hartner

IPC: G01S13/86 ,  G01S7/02 ,  H04B1/40

CPC classification number: G01S13/86 ,  G01S7/006 ,  G01S7/02 ,  G01S7/032 ,  G01S13/003 ,  G01S13/878 ,  G01S13/931 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H04B1/40

Abstract: A wireless communication system includes a first semiconductor module and a second semiconductor module. The first semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the first semiconductor module and the antenna structure of the first semiconductor module are arranged within a common package. The semiconductor die of the first semiconductor module includes a transmitter module configured to transmit the wireless communication signal through the antenna structure of the first semiconductor module. The second semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the second semiconductor module includes a receiver module configured to receive the wireless communication signal through the antenna structure of the second semiconductor module from the first semiconductor module.

Abstract translation: 无线通信系统包括第一半导体模块和第二半导体模块。 第一半导体模块包括连接到天线结构的半导体管芯。 第一半导体模块的半导体管芯和第一半导体模块的天线结构布置在公共封装内。 第一半导体模块的半导体管芯包括被配置为通过第一半导体模块的天线结构发送无线通信信号的发射器模块。 第二半导体模块包括连接到天线结构的半导体管芯。 第二半导体模块的半导体管芯包括：接收器模块，被配置为通过第二半导体模块的天线结构从第一半导体模块接收无线通信信号。

公开(公告)号：US20140141608A1

公开(公告)日：2014-05-22

申请号：US14166090

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.

Abstract translation: 一种制造具有半导体本体的半导体部件的方法，包括提供第一导电型的基板。 在基板上设置第二导电类型的掩埋半导体层。 功能单元半导体层设置在掩埋半导体层上。 至少一个到达衬底的沟槽形成在半导体本体中。 形成绝缘层，其覆盖沟槽的内壁，并使沟槽内部与功能单元半导体层和埋入半导体层电绝缘，绝缘层在沟槽底部的区域中具有至少一个开口。 所述至少一个沟槽填充有第一导电类型的导电半导体材料，其中所述导电半导体材料形成从所述半导体主体的表面到所述衬底的电接触。

公开(公告)号：US11387533B2

公开(公告)日：2022-07-12

申请号：US16032589

申请日：2018-07-11

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Dirk Hammerschmidt ,  Walter Hartner ,  Johannes Lodermeyer ,  Chiara Mariotti ,  Thorsten Meyer

IPC: G02B6/12 ,  H01P3/16 ,  H01Q3/44 ,  H01L23/66

Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.

公开(公告)号：US11145563B2

公开(公告)日：2021-10-12

申请号：US16447610

申请日：2019-06-20

Applicant: Infineon Technologies AG

Inventor： Christian Geissler ,  Walter Hartner ,  Claus Waechter ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

Abstract: A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

公开(公告)号：US10916484B2

公开(公告)日：2021-02-09

申请号：US16014745

申请日：2018-06-21

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Francesca Arcioni ,  Christian Geissler ,  Walter Hartner ,  Gerhard Haubner ,  Thorsten Meyer ,  Martin Richard Niessner ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

公开(公告)号：US20180374769A1

公开(公告)日：2018-12-27

申请号：US16014745

申请日：2018-06-21

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Francesca Arcioni ,  Christian Geissler ,  Walter Hartner ,  Gerhard Haubner ,  Thorsten Meyer ,  Martin Richard Niessner ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

公开(公告)号：US10008470B2

公开(公告)日：2018-06-26

申请号：US15628682

申请日：2017-06-21

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Walter Hartner

IPC: H01L21/00 ,  H01L21/4763 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538 ,  H01Q23/00 ,  H01Q1/22 ,  H01L23/522 ,  H01L23/498 ,  H01L23/66 ,  H01L25/16 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01Q1/2283 ,  H01Q23/00 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

公开(公告)号：US09922946B2

公开(公告)日：2018-03-20

申请号：US15480751

申请日：2017-04-06

Applicant: Infineon Technologies AG

Inventor： Ernst Seler ,  Maciej Wojnowski ,  Walter Hartner ,  Josef Boeck

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01Q13/08

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01Q13/08 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device package includes placing a semiconductor chip on a carrier, covering the semiconductor chip with an encapsulation material to form an encapsulation body, providing a microwave component having at least one electrically conducting wall structure integrated in the encapsulation body, and forming an electrical interconnect configured to electrically couple the semiconductor chip and the microwave component.

公开(公告)号：US09721920B2

公开(公告)日：2017-08-01

申请号：US13736097

申请日：2013-01-08

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Walter Hartner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L21/00 ,  H01L21/4763 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538 ,  H01Q23/00 ,  H01Q1/22 ,  H01L23/498 ,  H01L23/66 ,  H01L25/16 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L24/82 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01Q1/2283 ,  H01Q23/00 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

公开(公告)号：US09653426B2

公开(公告)日：2017-05-16

申请号：US15146090

申请日：2016-05-04

Applicant: Infineon Technologies AG

Inventor： Ernst Seler ,  Maciej Wojnowski ,  Walter Hartner ,  Josef Boeck

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01Q13/08 ,  H01L2924/00

Abstract: A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.