公开(公告)号：US20240114693A1

公开(公告)日：2024-04-04

申请号：US17958202

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher M. Neumann ,  Brian Doyle ,  Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Uygar E. Avci ,  Eungnak Han ,  Manish Chandhok ,  Nafees Aminul Kabir ,  Gurpreet Singh

IPC: H01L27/11514 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11504

CPC classification number: H01L27/11514 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11504

Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.

公开(公告)号：US11846883B2

公开(公告)日：2023-12-19

申请号：US16147131

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Robert Bristol ,  Marie Krysak ,  Lauren Doyle ,  James Blackwell ,  Eungnak Han

IPC: G03F7/039 ,  G03F7/004

CPC classification number: G03F7/039 ,  G03F7/0043 ,  G03F7/0045

Abstract: A photoresist is disclosed. The photoresist includes a polymer with one repeating unit and an absorbing unit.

公开(公告)号：US11837644B2

公开(公告)日：2023-12-05

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Richard Vreeland ,  Giselle Elbaz ,  Manish Chandhok ,  Richard E. Schenker ,  Gurpreet Singh ,  Florian Gstrein ,  Nafees Kabir ,  Tristan A. Tronic ,  Eungnak Han

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/7851

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20220199462A1

公开(公告)日：2022-06-23

申请号：US17511693

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Florian Gstrein ,  Eungnak Han ,  Marie Krysak ,  Tayseer Mahdi ,  Xuanxuan Chen ,  Brandon Jay Holybee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

公开(公告)号：US20220173034A1

公开(公告)日：2022-06-02

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US11137681B2

公开(公告)日：2021-10-05

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20210074632A1

公开(公告)日：2021-03-11

申请号：US16562346

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US10886175B2

公开(公告)日：2021-01-05

申请号：US16347507

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Rami Hourani ,  Florian Gstrein ,  Gurpreet Singh ,  Scott B. Clendenning ,  Kevin L. Lin ,  Manish Chandhok

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：US10269622B2

公开(公告)日：2019-04-23

申请号：US15529479

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Rami Hourani ,  Michael J. Leeson ,  Todd R. Younkin ,  Eungnak Han ,  Robert L. Bristol

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  G03F7/00 ,  G03F7/16 ,  H01L21/027

Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.

公开(公告)号：US20170207116A1

公开(公告)日：2017-07-20

申请号：US15480208

申请日：2017-04-05

Applicant: Intel Corporation

Inventor： Paul A. Nyhus ,  Eungnak Han ,  Swaminathan Sivakumar ,  Ernisse S. Putna

IPC: H01L21/768 ,  G03F7/004 ,  G03F7/20 ,  G03F7/039 ,  H01L21/3213 ,  G03F7/16 ,  G03F7/26 ,  H01L21/32 ,  H01L21/3105 ,  H01L21/3205 ,  G03F7/11 ,  G03F7/038

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.