公开(公告)号：US09281043B1

公开(公告)日：2016-03-08

申请号：US14582745

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Pulkit Jain ,  Fatih Hamzaoglu ,  Liqiong Wei

IPC: G11C11/00 ,  G11C11/16 ,  G06F12/02 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

Abstract translation: 描述了包括位线的装置。 该装置还包括耦合到位线的第一和第二存储单元。 第一存储单元具有第一存取晶体管。 第一存取晶体管耦合到第一线电阻。 第二存储单元具有第二存取晶体管。 第二存取晶体管耦合到第二线路电阻。 第二线电阻大于第一线电阻。 该装置还包括耦合到位线的第一和第二驱动器。 第二个驱动程序是比第一个驱动程序更强大的驱动程序。 该装置还包括选择第一驱动器以将信息写入第一存储单元并选择第二驱动器以将信息写入第二存储单元的电路。

公开(公告)号：US20250095693A1

公开(公告)日：2025-03-20

申请号：US18467947

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Van H. Le

IPC: G11C5/06 ,  G11C11/4091 ,  G11C11/419

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.

公开(公告)号：US12238913B2

公开(公告)日：2025-02-25

申请号：US18161915

申请日：2023-01-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H10B10/00 ,  G11C11/403 ,  H10B12/00

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20230397410A1

公开(公告)日：2023-12-07

申请号：US17834679

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Juan Alzate Vinasco ,  Liqiong Wei ,  Ozdemir Akin ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4091

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  G11C11/4085 ,  G11C11/4091

Abstract: Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.

公开(公告)号：US20230371233A1

公开(公告)日：2023-11-16

申请号：US17742628

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Forough Mahmoudabadi ,  Shailesh Kumar Madisetti ,  Van H. Le ,  Timothy Jen ,  Cheng Tan ,  Jisoo Kim ,  Miriam R. Reshotko ,  Vishak Venkatraman ,  Eva Vo ,  Yue Zhong ,  Yu-Che Chiu ,  Moshe Dolejsi ,  Lorenzo Ferrari ,  Akash Kannegulla ,  Deepyanti Taneja ,  Mark Armstrong ,  Kamal H. Baloch ,  Afrin Sultana ,  Albert B. Chen ,  Vamsi Evani ,  Yang Yang ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L27/10805 ,  H01L23/5283 ,  H01L29/78696 ,  H01L29/94

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

公开(公告)号：US11024356B2

公开(公告)日：2021-06-01

申请号：US16565299

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C13/00 ,  G11C29/02

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20200091156A1

公开(公告)日：2020-03-19

申请号：US16133655

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/11 ,  H01L27/108 ,  G11C11/403

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US09978447B2

公开(公告)日：2018-05-22

申请号：US15496655

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

IPC: G11C11/419 ,  G11C11/413 ,  G11C11/417 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

公开(公告)号：US09922691B2

公开(公告)日：2018-03-20

申请号：US15062073

申请日：2016-03-05

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Fatih Hamzaoglu ,  Liqiong Wei

IPC: G11C11/00 ,  G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

公开(公告)号：US09805790B2

公开(公告)日：2017-10-31

申请号：US15025229

申请日：2013-12-05

Applicant: Intel Corporation

Inventor： Nathaniel J. August ,  Pulkit Jain ,  Stefan Rusu ,  Fatih Hamzaoglu ,  Rangharajan Venkatesan ,  Muhammad Khellah ,  Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz ,  Yih Wang

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.