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    VOLTAGE LEVEL SHIFTER CIRCUIT
    26.
    发明申请
    VOLTAGE LEVEL SHIFTER CIRCUIT 审中-公开
    电压水平更换电路

    公开(公告)号：US20160294394A1

    公开(公告)日：2016-10-06

    申请号：US15182486

    申请日：2016-06-14

    Applicant: INTEL CORPORATION

    Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

    IPC: H03K19/0185

    CPC classification number: H03K19/018521 ,  H03K3/356113

    Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

    Abstract translation: 实施例包括用于在低电压域和高电压域之间电压移位数据信号的装置，方法和系统。 在实施例中，电压电平移位器电路可以包括自适应保持器电路，增强的可中断电源电路和/或电容升压电路，以减小由电压电平移位器电路支持的低电压域的最小电压。 可以描述和要求保护其他实施例。

    ASSIST CIRCUIT FOR MEMORY
    27.
    发明申请
    ASSIST CIRCUIT FOR MEMORY 审中-公开

    公开(公告)号：US20160225419A1

    公开(公告)日：2016-08-04

    申请号：US15094755

    申请日：2016-04-08

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    IPC: G11C7/12 ,  G11C7/22

    CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

    Assist circuit for memory
    28.
    发明授权
    Assist circuit for memory 有权
    辅助电路用于记忆

    公开(公告)号：US09355694B2

    公开(公告)日：2016-05-31

    申请号：US14229767

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    IPC: G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C17/16

    CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

    Abstract translation: 实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。 例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。 辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。 另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。 辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

    REDUCED SWING BIT-LINE APPARATUS AND METHOD
    30.
    发明申请
    REDUCED SWING BIT-LINE APPARATUS AND METHOD 有权

    公开(公告)号：US20170270998A1

    公开(公告)日：2017-09-21

    申请号：US15072278

    申请日：2016-03-16

    Applicant: Intel Corporation

    Inventor： Jaydeep P. Kulkarni ,  Iqbal R. Rajwani ,  Eric K. Donkoh

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.

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