公开(公告)号：US20210398977A1

公开(公告)日：2021-12-23

申请号：US16905743

申请日：2020-06-18

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Peng Zheng ,  Aaron Lilak ,  Tahir Ghani ,  Harold Kennel ,  Mauro Kobrinsky

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L27/11 ,  H01L21/8238

Abstract: Integrated circuitry comprising interconnect metallization on both front and back sides of a gate-all-around (GAA) transistor structure lacking at least one active bottom channel region. Bottom channel regions may be depopulated from a GAA transistor structure following removal of a back side substrate that exposes an inactive portion of a semiconductor fin. During back-side processing, one or more bottom channel region may be removed or rendered inactive through dopant implantation. Back-side processing may then proceed with the interconnection of one or more terminal of the GAA transistor structures through one or more levels of back-side interconnect metallization.

公开(公告)号：US10685949B2

公开(公告)日：2020-06-16

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H05K1/14 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US20240332379A1

公开(公告)日：2024-10-03

申请号：US18129688

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shaun Mills ,  Ehren Mannebach ,  Mauro Kobrinsky ,  Kai Loon Cheong ,  Makram Abd El Qader

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775

Abstract: Devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside contact etch prior to cavity spacer formation. A transistor includes semiconductor structures such as nanoribbons extending between a source and a drain. A spacer material is between a gate and the source/drain as cavity spacer fill. The spacer material is also between a portion of a backside contact and a portion of the source/drain, to eliminate a short between the backside contact and the gate.

公开(公告)号：US12107170B2

公开(公告)日：2024-10-01

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/7869

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US20240006302A1

公开(公告)日：2024-01-04

申请号：US17856777

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Richard H. Livengood ,  Muhammad Usman Raza ,  Waqas Ali ,  Tahir Malik ,  Shida Tan ,  Martin Von Haartman ,  Mauro Kobrinsky ,  Amir Raveh ,  Clifford J. Engle

IPC: H01L23/50 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/50 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0873 ,  H01L29/42392 ,  H01L29/78696

Abstract: Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.

公开(公告)号：US20230197601A1

公开(公告)日：2023-06-22

申请号：US17558423

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jiun-Ruey Chen ,  Christopher Jezewski ,  John Plombon ,  Miriam Reshotko ,  Mauro Kobrinsky ,  Scott B. Clendenning

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/5328 ,  H01L23/53238 ,  H01L21/76879 ,  H01L21/76807

Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

公开(公告)号：US20220415818A1

公开(公告)日：2022-12-29

申请号：US17358962

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Jasmeet Chawla ,  Matthew Metz ,  Sean King ,  Ramanan Chebiam ,  Mauro Kobrinsky ,  Scott Clendenning ,  Sudarat Lee ,  Christopher Jezewski ,  Sunny Chugh ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768

Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

公开(公告)号：US11276644B2

公开(公告)日：2022-03-15

申请号：US16221798

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L23/532 ,  H01L29/45 ,  H01L29/786 ,  H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L21/285

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US20210407895A1

公开(公告)日：2021-12-30

申请号：US16914132

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC: H01L23/498 ,  H01L21/768 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H01L27/088

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

公开(公告)号：US11171239B2

公开(公告)日：2021-11-09

申请号：US16570965

申请日：2019-09-13

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,