公开(公告)号：US11449446B2

公开(公告)日：2022-09-20

申请号：US16936078

申请日：2020-07-22

Applicant: Intel Corporation

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F13/40 ,  G06F13/28 ,  G06F12/0866 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F13/42 ,  G06F13/10

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

公开(公告)号：US11144387B2

公开(公告)日：2021-10-12

申请号：US16398076

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  William A. Stevens, Jr. ,  Michael T. Klinglesmith ,  Mikal Hunsaker

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/42

Abstract: Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a memory device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a memory device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.

公开(公告)号：US10133670B2

公开(公告)日：2018-11-20

申请号：US14583611

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Jose S. Niell ,  Michael T. Klinglesmith ,  Derek T. Bachand ,  Ganesh Kumar

IPC: G06F12/0815 ,  G06F13/28 ,  G06F13/42

Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

公开(公告)号：US09658978B2

公开(公告)日：2017-05-23

申请号：US14209184

申请日：2014-03-13

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Robert P. Adler

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/364 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0026

Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

公开(公告)号：US20160357696A1

公开(公告)日：2016-12-08

申请号：US14865005

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Michael T. Klinglesmith ,  Mikal C. Hunsaker ,  William Knolla ,  Hartej Singh

IPC: G06F13/40

CPC classification number: G06F13/4068

Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括：经由与第一根空间和第二根空间相关联的多根代理的边带接口接收复位准备信号以通知多根代理第一根空间为 复位; 通过边带接口发送确认复位准备信号的确认信号; 从耦合到所述多根代理的结构接收用于所述第一根空间的一个或多个事务; 以及响应于重置准备信号终止一个或多个事务，其中当接收到一个或多个事务时，第一根空间处于复位状态。 描述和要求保护其他实施例。

公开(公告)号：US20160335208A1

公开(公告)日：2016-11-17

申请号：US15224006

申请日：2016-07-29

Applicant: Intel Corporation

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G06F3/06 ,  G06F13/10

CPC classification number: G06F13/28 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0673 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F12/0866 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/262 ,  G06F2213/0026 ,  G06F2213/0032

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. For instance, there is disclosed a storage apparatus having therein a plurality of NAND (Negated AND) based flash memory components arranged into a plurality of NAND arrays; a NAND controller communicatively interfaced with the plurality of NAND arrays; and block mirroring logic to establish a mirrored copy for each data block written to the storage apparatus, each mirrored copy to be stored within one of plurality of NAND arrays. Other related embodiments are disclosed.

Abstract translation: 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。 例如，公开了一种存储装置，其中具有排列成多个NAND阵列的多个基于NAND（Negated AND）的闪速存储器组件; 与多个NAND阵列通信地对接的NAND控制器; 和块镜像逻辑，以便为写入存储设备的每个数据块建立镜像拷贝，每个镜像拷贝存储在多个NAND阵列之一内。 公开了其他相关实施例。

公开(公告)号：US09489329B2

公开(公告)日：2016-11-08

申请号：US14209146

申请日：2014-03-13

Applicant: INTEL CORPORATION

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Rohit R. Verma

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/364 ,  G06F13/362 ,  G06F15/16 ,  G06F9/44

CPC classification number: G06F13/364 ,  G06F9/44 ,  G06F13/362 ,  G06F15/16

Abstract: In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从结构中的第一代理接收对交易的请求并获得交易的地址，请求者标识符，标签和业务类别的方法，以及确定 基于至少两个地址，请求者标识符，标签和流量类来接收交易的目标代理。 基于此通道确定，可以将事务发送到目标代理的通道。 描述和要求保护其他实施例。

公开(公告)号：US09448870B2

公开(公告)日：2016-09-20

申请号：US14503637

申请日：2014-10-01

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Rohit R. Verma

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/42

CPC classification number: G06F11/0772 ,  G06F11/0784 ,  G06F11/0793 ,  G06F13/4221

Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种处理在根据使用PCI Express™语义的外围组件互连（PCI）规范设计的代理中接收到的请求的方法。 更具体地，响应于确定代理不支持请求，可以更新代理的不支持的请求检测注册器，以及从代理发送的指示代理不支持该请求的响应。 描述和要求保护其他实施例。

公开(公告)号：US20160132447A1

公开(公告)日：2016-05-12

申请号：US15001330

申请日：2016-01-20

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Mohan K. Nair ,  Joseph Murray ,  Rohit R. Verma ,  Gary J. Lavelle ,  Robert P. Adler

IPC: G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/385 ,  G06F13/4265 ,  G06F15/7807 ,  G06F15/7825 ,  G06F2213/0038 ,  H04L12/28 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。 反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。 然后，路由器可以将聚合完成发送到第一个端点。 描述和要求保护其他实施例。

公开(公告)号：US09270576B2

公开(公告)日：2016-02-23

申请号：US14209207

申请日：2014-03-13

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Mohan K. Nair ,  Joseph Murray ,  Rohit R. Verma ,  Gary J. Lavelle ,  Robert P. Adler

IPC: H04L12/761 ,  H04L12/28 ,  H04L12/54 ,  H04L12/701 ,  G06F15/78 ,  G06F13/38

CPC classification number: G06F13/364 ,  G06F13/385 ,  G06F13/4265 ,  G06F15/7807 ,  G06F15/7825 ,  G06F2213/0038 ,  H04L12/28 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。 反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。 然后，路由器可以将聚合完成发送到第一个端点。 描述和要求保护其他实施例。