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公开(公告)号：US10095302B2
公开(公告)日：2018-10-09
申请号：US15250123
申请日：2016-08-29
Applicant: Intel Corporation
Inventor： Ariel Gur , Daniel J Ragland , Ofer Nathan , Nadav Shulman , Esfir Natanzon
IPC: G06F1/32
Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.
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公开(公告)号：US20180059748A1
公开(公告)日：2018-03-01
申请号：US15702970
申请日：2017-09-13
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Doron Rajwan , Dorit Shapira , Nadav Shulman , Tomer Ziv
CPC classification number: G06F1/206 , G01K1/026 , G01K13/00 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F9/5094
Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
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公开(公告)号：US09760158B2
公开(公告)日：2017-09-12
申请号：US14298171
申请日：2014-06-06
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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公开(公告)号：US09535812B2
公开(公告)日：2017-01-03
申请号：US13930212
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Doron Rajwan , Nadav Shulman , Dorit Shapira , Kosta Luria , Efraim Rotem
CPC classification number: G06F11/3037 , G06F11/3419 , G06F11/3476 , G06F2201/88
Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括用于测量与处理器相关联的使用的测量逻辑。 处理器还包括用于基于统计过程来确定是否提供响应于使用已经增加了定义量的指示来记录使用增加的许可的统计逻辑。 处理器还包括控制逻辑，用于响应于从统计逻辑接收到记录的许可而记录在非易失性存储器中的定义的使用增加。 描述和要求保护其他实施例。
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公开(公告)号：US20160147275A1
公开(公告)日：2016-05-26
申请号：US14554628
申请日：2014-11-26
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Hisham Abu Salah , Efraim Rotem , Guy M. Therien , Nadav Shulman , Esfir Natanzon , Paul S. Diefenbaugh
CPC classification number: G06F1/3206 , G06F1/206 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括用于执行指令的一个或多个核和耦合到所述一个或多个核的功率控制器。 反过来，功率控制器包括控制逻辑，用于从一个或多个源接收动态变化到一个或多个核中的至少一个运行的保证频率的指示，以及确定最终保证 处理器要为下一个窗口操作的频率，以及将最终保证频率传送到至少一个实体。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US09268378B2
公开(公告)日：2016-02-23
申请号：US13931128
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Efraim Rotem , Alon Naveh , Doron Rajwan , Nadav Shulman , Eliezer Weissmann
CPC classification number: G06F1/206 , G06F1/203 , G06F1/3206 , G06F1/3215 , G06F1/3243 , G06F1/3287 , Y02D10/16 , Y02D10/171 , Y02D50/20
Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.
Abstract translation: 在一个实施例中，一种装置包括温度传感器，用于对平台中的部件执行多个结温测量，控制器包括至少其一部分处于硬件中的逻辑。 逻辑可以从温度传感器接收多个结温度测量值，并且当结温度测量超过第一阈值时可以指示组件执行部件的第一次掉电动作，并且可以指示组件执行第二次掉电 当基于结温度测量的多重性的平均结温超过第二阈值时，组分的作用。 公开和要求保护其他实施例。
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公开(公告)号：US20240411339A1
公开(公告)日：2024-12-12
申请号：US18659807
申请日：2024-05-09
Applicant: Intel Corporation
Inventor： Daniel Ragland , Nadav Shulman , Louis Draghi
IPC: G06F1/10 , G06F1/08 , G06F1/20 , G06F1/3206 , G06F16/9035
Abstract: Methods, apparatus, and articles of manufacture to dynamically configure overclocking frequency have been disclosed. An example apparatus include a clock rate adjuster to cause a processor core to operate at a first overclocked clock rate; a comparator to compare a sensed temperature corresponding to the processor core to a threshold; and the clock rate adjuster to, when the sensed temperature satisfies the threshold, decrease a clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the decreased clock rate being above a normal operating clock rate of the processor core.
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公开(公告)号：US20240231465A9
公开(公告)日：2024-07-11
申请号：US17969524
申请日：2022-10-19
Applicant: Intel Corporation
Inventor： Yoav Babajani , Hisham Abu Salah , Nadav Shulman , Nir Misgav , Arik Gihon
IPC: G06F1/324 , G06F1/3206
CPC classification number: G06F1/324 , G06F1/3206
Abstract: Embodiments herein relate to a technique to be performed by a power control unit (PCU) of an electronic device. Specifically, the PCU may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. Based on these weights, the PCU may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. Other embodiments may be described and claimed.
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公开(公告)号：US20240134440A1
公开(公告)日：2024-04-25
申请号：US17969524
申请日：2022-10-18
Applicant: Intel Corporation
Inventor： Yoav Babajani , Hisham Abu Salah , Nadav Shulman , Nir Misgav , Arik Gihon
IPC: G06F1/324 , G06F1/3206
CPC classification number: G06F1/324 , G06F1/3206
Abstract: Embodiments herein relate to a technique to be performed by a power control unit (PCU) of an electronic device. Specifically, the PCU may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. Based on these weights, the PCU may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. Other embodiments may be described and claimed.
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公开(公告)号：US10921872B2
公开(公告)日：2021-02-16
申请号：US16369136
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Elkana Korem , Hanan Shomroni , Nadav Shulman
IPC: G06F1/324 , G06F1/3287 , G06F1/3234 , G06F1/3293 , G06F1/329
Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.
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