公开(公告)号：US20210296315A1

公开(公告)日：2021-09-23

申请号：US16827566

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Ehren MANNEBACH ,  Patrick MORROW ,  Willy RACHMADY

IPC: H01L27/092 ,  H01L29/10 ,  H01L23/498 ,  H01L23/528

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20210091080A1

公开(公告)日：2021-03-25

申请号：US16772636

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8254

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).

公开(公告)号：US20200381525A1

公开(公告)日：2020-12-03

申请号：US16999508

申请日：2020-08-21

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20200227396A1

公开(公告)日：2020-07-16

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Ravi PILLARISETTY ,  Kimin JUN ,  Patrick MORROW ,  Valluri R. RAO ,  Paul B. FISCHER ,  Robert S. CHAU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US20190172950A1

公开(公告)日：2019-06-06

申请号：US16323661

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Sean T. MA ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Stephen M. CEA

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.

公开(公告)号：US20180315838A1

公开(公告)日：2018-11-01

申请号：US15770463

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L29/66 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L29/66439 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20180219090A1

公开(公告)日：2018-08-02

申请号：US15747423

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

IPC: H01L29/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L29/78 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20170229565A1

公开(公告)日：2017-08-10

申请号：US15329216

申请日：2014-09-09

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Sansaptak DASGUPTA ,  Alejandro X. LEVANDER ,  Patrick MORROW

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7781 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66545

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.

公开(公告)号：US20170221901A1

公开(公告)日：2017-08-03

申请号：US15490754

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Kimin JUN ,  Patrick MORROW

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10832 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/20 ,  H01L28/87 ,  H01L28/91 ,  H01L29/945

Abstract: Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.