公开(公告)号：US20170133462A1

公开(公告)日：2017-05-11

申请号：US15410649

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200227520A1

公开(公告)日：2020-07-16

申请号：US16831692

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200152797A1

公开(公告)日：2020-05-14

申请号：US16740089

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/268 ,  H01L29/78

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US20200035818A1

公开(公告)日：2020-01-30

申请号：US16592380

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Cory E. WEBER ,  Patrick H. KEYS ,  Seiyon KIM ,  Michael G. HAVERTY ,  Sadasivan SHANKAR

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

公开(公告)号：US20190214461A1

公开(公告)日：2019-07-11

申请号：US16358613

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/786 ,  H01L21/3115

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20180261498A1

公开(公告)日：2018-09-13

申请号：US15779442

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

公开(公告)号：US20180226496A1

公开(公告)日：2018-08-09

申请号：US15771998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/267 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/107 ,  H01L29/1079 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

公开(公告)号：US20160276484A1

公开(公告)日：2016-09-22

申请号：US15024714

申请日：2013-12-19

Applicant: INTEL CORPORATION

Inventor： Seiyon KIM ,  Rafael RIOS ,  Fahmida FERDOUSI ,  Kelin J. KUHN

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

Abstract translation: 描述了具有基于混合几何的有源区域的非平面半导体器件。 例如，半导体器件包括混合沟道区域，其包括设置在鳍状FET部分上方的Ω-FET部分上方的纳米线部分。 栅极叠层设置在混合沟道区域的暴露表面上。 栅极堆叠包括栅极电介质层和设置在栅极介电层上的栅电极。 源极和漏极区域设置在混合沟道区域的两侧。

公开(公告)号：US20150303258A1

公开(公告)日：2015-10-22

申请号：US14789856

申请日：2015-07-01

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L27/12 ,  H01L29/165 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。