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    Selective memory mode authorization enforcement
    21.
    发明授权
    Selective memory mode authorization enforcement 有权

    公开(公告)号：US10379768B2

    公开(公告)日：2019-08-13

    申请号：US15283074

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： Mahesh S. Natu ,  Vedaraman Geetha

    IPC: G06F3/06 ,  G06F12/14 ,  G06F12/0802 ,  G06F12/0868

    Abstract: In one embodiment, a memory interface employs selective memory mode authorization enforcement in accordance with the present description to ensure that memory modes of operation which have not been authorized, are not permitted to proceed. In one embodiment, mode control logic receives from memory control logic of the memory interface, memory mode selection data which is compared to a mode authorization classification structure to determine if the memory mode being selected in association with a memory transaction request is authorized or otherwise permitted. Memory mode enablement logic of the mode control logic enables the requested memory mode associated with a memory transaction request if it is determined that the selected memory mode associated with the memory transaction request is authorized. Other aspects are described herein.

    Two level memory full line writes
    23.
    发明授权
    Two level memory full line writes 有权

    公开(公告)号：US09619396B2

    公开(公告)日：2017-04-11

    申请号：US14670857

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/00 ,  G06F12/0891

    CPC classification number: G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126 ,  G06F2212/1016

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

    TWO LEVEL MEMORY FULL LINE WRITES
    24.
    发明申请
    TWO LEVEL MEMORY FULL LINE WRITES 有权
    两级记忆全线写

    公开(公告)号：US20160283388A1

    公开(公告)日：2016-09-29

    申请号：US14670857

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126 ,  G06F2212/1016

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

    Abstract translation: 存储器控制器接收存储器无效请求，该存储器无效请求引用具有远存储器和近存储器的两级系统存储器拓扑中的远存储器行，标识对应于该行的近存储器的地址，并且在地址处读取数据以确定是否 该行的副本在近内存中。 如果数据包含远端存储器的另一行的副本，而另一行的副本是脏的，则该地址的数据将被刷新到远端存储器。 发送内存无效请求的完成以指示相干代理被授予对该行的独占访问权限。 通过独占访问，将修改该行以生成行的修改版本，并且将使用修改版本的行覆盖近端存储器的地址。

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