公开(公告)号：US11362082B2

公开(公告)日：2022-06-14

申请号：US16016419

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Paul Fischer ,  Walid Hafez ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L27/02 ,  H01L29/10 ,  H01L23/62 ,  H01L21/265 ,  H01L27/06

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

公开(公告)号：US11239149B2

公开(公告)日：2022-02-01

申请号：US15942952

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Uddalak Bhattacharya ,  Zhanping Chen ,  Walid Hafez

IPC: G11C11/00 ,  H01L23/50 ,  H01L21/768 ,  H01L21/77

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US10761264B2

公开(公告)日：2020-09-01

申请号：US16462077

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid Hafez ,  Neville Dias ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/00 ,  H01P3/16 ,  G02B6/134 ,  G02B6/136

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

公开(公告)号：US10192969B2

公开(公告)日：2019-01-29

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L23/535 ,  H01L23/66 ,  H01L21/3115

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US12080763B2

公开(公告)日：2024-09-03

申请号：US17826058

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L21/033 ,  H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/0337 ,  H01L21/28575 ,  H01L21/3212 ,  H01L21/76802 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/778

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

公开(公告)号：US11688788B2

公开(公告)日：2023-06-27

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/28158 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US11664417B2

公开(公告)日：2023-05-30

申请号：US16130911

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8236 ,  H01L29/51 ,  H01L29/20

CPC classification number: H01L29/0638 ,  H01L21/8236 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/51

Abstract: Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC.

公开(公告)号：US11489061B2

公开(公告)日：2022-11-01

申请号：US16139248

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dusgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.

公开(公告)号：US11387329B2

公开(公告)日：2022-07-12

申请号：US16147275

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L27/088 ,  H01L29/778

Abstract: Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.

公开(公告)号：US11387327B2

公开(公告)日：2022-07-12

申请号：US16144946

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L21/285 ,  H01L29/778 ,  H01L21/033 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L21/321

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.