公开(公告)号：US20180182696A1

公开(公告)日：2018-06-28

申请号：US15900696

申请日：2018-02-20

Applicant: INTEL CORPORATION

Inventor： Sanka GANESAN ,  Zhiguo QIAN ,  Robert L. SANKMAN ,  Krishna SRINIVASAN ,  Zhaohui ZHU

IPC: H01L23/498 ,  H01L23/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20230317588A1

公开(公告)日：2023-10-05

申请号：US17707342

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Jiwei SUN ,  Zhiguo QIAN ,  Kemal AYGÜN

IPC: H01L23/498 ,  H01L23/66

CPC classification number: H01L23/49827 ,  H01L2223/6616 ,  H01L23/66 ,  H01L23/49838

Abstract: Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.

公开(公告)号：US20230238332A1

公开(公告)日：2023-07-27

申请号：US18128960

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/5381 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/13 ,  H01L23/53295 ,  H01L24/81 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/49822 ,  H01L21/4846 ,  H01L23/3128 ,  H01L21/486 ,  H01L23/5226 ,  H01L24/17 ,  H01L2224/81

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20220130742A1

公开(公告)日：2022-04-28

申请号：US17566523

申请日：2021-12-30

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC: H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20210125912A1

公开(公告)日：2021-04-29

申请号：US16666202

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG ,  Brandon C. MARIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US20200381350A1

公开(公告)日：2020-12-03

申请号：US16636620

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US20200235053A1

公开(公告)日：2020-07-23

申请号：US16634864

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20180331036A1

公开(公告)日：2018-11-15

申请号：US15773950

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC: H01L23/528 ,  H01L23/66 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H01L23/00 ,  H01R13/6471

CPC classification number: H01L23/5286 ,  H01L21/4857 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/17 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R13/6471 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.