公开(公告)号：US11837549B2

公开(公告)日：2023-12-05

申请号：US18089542

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US11817391B2

公开(公告)日：2023-11-14

申请号：US18128960

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20230230923A1

公开(公告)日：2023-07-20

申请号：US17824974

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Gerald Pasdast ,  Zhiguo Qian ,  Sathya Narasimman Tiagaraj ,  Lakshmipriya Seshan ,  Peipei Wang ,  Debendra Das Sharma ,  Srikanth Nimmagadda ,  Zuoguo Wu ,  Swadesh Choudhary ,  Narasimha Lanka

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/5382 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16225

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

公开(公告)号：US11694952B2

公开(公告)日：2023-07-04

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US11621227B2

公开(公告)日：2023-04-04

申请号：US17540141

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/52 ,  H01L21/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20230088928A1

公开(公告)日：2023-03-23

申请号：US17483444

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jung Kyu Han ,  Jiwei Sun ,  Zhiguo Qian ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L23/15 ,  H01L49/02 ,  H01L21/48

Abstract: Embedded glass cores in package substrates and related methods are disclosed herein including an integrated circuit including a substrate having a first side and a second side opposite the first side, a plurality of vias disposed within the substrate to electrically couple corresponding contacts on the first and second sides of the substrate, a glass core surrounding a first via of the plurality of vias, and an organic core surrounding a second via of the plurality of vias, the second via different than the first via.

公开(公告)号：US11545416B2

公开(公告)日：2023-01-03

申请号：US16643816

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Jianyong Xie ,  Yidnekachew S. Mekonnen ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

公开(公告)号：US11450613B2

公开(公告)日：2022-09-20

申请号：US15933934

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Mayue Xie ,  Jong-Ru Guo ,  Zhiguo Qian ,  Zuoguo Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/58 ,  G01R31/28

Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.

公开(公告)号：US20220270974A1

公开(公告)日：2022-08-25

申请号：US17684163

申请日：2022-03-01

Applicant: INTEL CORPORATION

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/762 ,  H01L21/765 ,  H01L25/065 ,  H01L29/06

Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220102259A1

公开(公告)日：2022-03-31

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.