公开(公告)号：US20180299940A1

公开(公告)日：2018-10-18

申请号：US15487550

申请日：2017-04-14

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  James Hermerding, II

IPC: G06F1/32 ,  G06F15/78 ,  G06F9/50 ,  G06F1/20

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to monitor and manage usage of resources on a computing platform. An example apparatus includes a processor and a subsystem. The example processor includes a modified operating system, the operating system modified to monitor application execution via the processor to determine a usage scenario for the apparatus. The example processor includes an index generator to generate a system usage scenario index quantifying a snapshot of the usage scenario for the processor and the subsystem of the apparatus. The example processor includes a rebalancer to reallocate resources of at least one of the processor or the subsystem based on the system usage scenario index.

公开(公告)号：US20250123675A1

公开(公告)日：2025-04-17

申请号：US18990429

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  Ho Jeong An ,  Nisha Aram ,  Sravya Atluri ,  Simonjit Dutta ,  Darwin Guo ,  Linlin Hou ,  Yishin Huang ,  Ho Kyu Kang ,  Brice Onken ,  Veeraraghavan Ramaraj ,  Cameron Rieck ,  Malavika Srinivas ,  Venkateshan Udhayan ,  Fidel Angel Vanegas Patino ,  Zhongsheng Wang ,  Ulises Zaragoza

IPC: G06F1/3296

Abstract: A component of a computing system, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processor circuitry, cause the processor circuitry to: dynamically monitor runtime metrics across processor cores of the computing system, wherein the runtime metrics comprise a measure of system-critical task residency and a measure of user-critical foreground application utilization; and initiate a power optimization action configured to transition the computing system into a power efficiency mode when the system-critical task residency is below a system-critical task residency threshold and the user-critical foreground application utilization is below a user-critical foreground application utilization threshold.

公开(公告)号：US12117886B2

公开(公告)日：2024-10-15

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US20240330050A1

公开(公告)日：2024-10-03

申请号：US18193127

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Madhusudan Chidambaram ,  Efraim Rotem ,  Stephen H. Gunther ,  Rajshree Chabukswar ,  Zhongsheng Wang

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4893 ,  G06F9/5094

Abstract: Embodiments herein relate to selecting cores in a processor using a core mask. In one aspect, a computing device includes different types of cores arranged in one or more processors. The core types are different in terms of performance and power consumption. A core mask is provided which indicates the number of cores which are selected to be active for each core type. A driver can receive a gear setting, which represents a first preference for higher performance or reduced power consumption. A slider value, which represents a second preference for higher performance or reduced power consumption, is provided based on the gear setting and a core utilization percentage and/or foreground activity percentage. A core mask is selected based on the slider value and the current workload type. The first preference can guide, without dictating, a decision of which cores are selected.

公开(公告)号：US20240220446A1

公开(公告)日：2024-07-04

申请号：US18149072

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Zhongsheng Wang ,  Russell Fenger ,  Asit Kumar Verma ,  DK Deepika ,  Yevgeni Sabin ,  Daniel J. Rogers ,  Cameron T. Rieck

IPC: G06F15/80 ,  G06F9/48

CPC classification number: G06F15/80 ,  G06F9/48

Abstract: Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).

公开(公告)号：US11650648B2

公开(公告)日：2023-05-16

申请号：US16914029

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Maximilian Domeika ,  Soethiha Soe ,  James Hermerding, II ,  Zhongsheng Wang ,  Wessam Elhefnawy ,  Efraim Rotem ,  Christopher Joseph Binns

IPC: G06F1/32 ,  G06F11/30 ,  G06K9/62 ,  G06F1/3212 ,  G06F1/3296

CPC classification number: G06F1/3212 ,  G06F1/3296 ,  G06F11/3062 ,  G06F11/3075 ,  G06K9/6262

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve computing device power management. An example apparatus includes a usage classifier to classify usage of a computing system, a low battery probability determiner to determine a probability of the computing system operating with a low battery capacity based on the classification, a policy reward determiner to determine an adjustment of a policy based on at least one of the classification or the probability, and determine a battery capacity of the computing system in response to the adjustment, and a policy adjustor to adjust the policy in response to the battery capacity satisfying a threshold.

公开(公告)号：US11592888B2

公开(公告)日：2023-02-28

申请号：US17306778

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  James Hermerding, II ,  Zhongsheng Wang ,  Pranava Alekal

IPC: G06F1/00 ,  G06F1/3203 ,  H04W92/18

Abstract: Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.

公开(公告)号：US20220334631A1

公开(公告)日：2022-10-20

申请号：US17856470

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  James Hermerding, II

IPC: G06F1/3206 ,  G06F15/78 ,  G06F9/50 ,  G06F1/20 ,  G06F1/324 ,  G06F15/76

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to monitor and manage usage of resources on a computing platform. An example apparatus includes a processor and a subsystem. The example processor includes a modified operating system, the operating system modified to monitor application execution via the processor to determine a usage scenario for the apparatus. The example processor includes an index generator to generate a system usage scenario index quantifying a snapshot of the usage scenario for the processor and the subsystem of the apparatus. The example processor includes a rebalancer to reallocate resources of at least one of the processor or the subsystem based on the system usage scenario index.

公开(公告)号：US20220326096A1

公开(公告)日：2022-10-13

申请号：US17850561

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Smit Kapila ,  Abhishek Srivastav ,  Sumod Cherukkate ,  Manit Biswas ,  Zhongsheng Wang ,  Bijendra Singh ,  Deepak Ganapathy ,  Dipen Dudhat

IPC: G01K11/22 ,  H05K7/20

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to monitor thermal degradation of a compute device. One such method includes calculating, by executing instructions with processor circuitry, a thermal degradation value based on an equation, the equation generated based on testing of thermal interface materials having varying degrees of degradation. The method also includes comparing, by executing instructions with the processor circuitry, the thermal degradation value to a thermal degradation threshold to determine whether the thermal degradation threshold is satisfied, and, when the thermal degradation threshold is satisfied, triggering generation of a thermal degradation alert.

公开(公告)号：US11249537B2

公开(公告)日：2022-02-15

申请号：US16927649

申请日：2020-07-13

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Eugene Gorbatov ,  Zhongsheng Wang ,  James G. Hermerding, II ,  Basavaraj B. Astekar ,  Jenn Chuan Cheng ,  Chia-Hung Sophia Kuo ,  Ashwin Umapathy ,  Tin-Cheung Kung ,  Yifan Li ,  Alexander B. Uan-Zo-Li

IPC: G06F1/324 ,  G06F1/3287 ,  G06F13/38 ,  G06F13/42 ,  G06F1/26 ,  G06F1/3296 ,  G06F1/3215 ,  G06F13/40

Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.