公开(公告)号：US20170170321A1

公开(公告)日：2017-06-15

申请号：US15445287

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/322 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/165

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

公开(公告)号：US20170170302A1

公开(公告)日：2017-06-15

申请号：US15445344

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L29/165 ,  H01L29/78 ,  H01L21/322

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/322 ,  H01L21/3221 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

公开(公告)号：US20170117300A1

公开(公告)日：2017-04-27

申请号：US15397170

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/308 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

公开(公告)号：US20170098665A1

公开(公告)日：2017-04-06

申请号：US15381441

申请日：2016-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L27/12 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L21/84 ,  H01L21/308

CPC classification number: H01L27/1211 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

公开(公告)号：US09608068B2

公开(公告)日：2017-03-28

申请号：US14819244

申请日：2015-08-05

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Hong He ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/76254 ,  H01L29/7842

Abstract: A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer. The silicon device layer has a tensily-strained region overlying the silicon-germanium feature. Regions of the silicon device layer not overlying the silicon-germanium feature are less strained than the tensily-strained region. The tensily-strained region of the silicon device layer may be further processed into channel features in n-type field effect transistors with improved charge carrier mobilities and device drive currents.

公开(公告)号：US20170076992A1

公开(公告)日：2017-03-16

申请号：US14851838

申请日：2015-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/823821 ,  H01L21/823878 ,  H01L27/1211

Abstract: A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices, and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate.

Abstract translation: 一种用于形成半导体器件的方法包括将第一鳍片蚀刻成体半导体衬底，并使第一鳍片的一部分通过形成在第一鳍片上的第一介电层暴露。 第一膜沉积在用于n型器件的区域中的第一鳍片上，并且第二膜沉积在用于p型器件的区域中的第一鳍片上。 蚀刻第一膜和第二膜以在n型器件的区域和用于p型器件的区域中形成第二鳍。 第二个翅片被保护。 从第一电介质层移除第一散热片以形成将第二散热片与衬底隔开的隔离层。

公开(公告)号：US20170053838A1

公开(公告)日：2017-02-23

申请号：US14833350

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US09576979B2

公开(公告)日：2017-02-21

申请号：US14722237

申请日：2015-05-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L21/308 ,  H01L27/12 ,  H01L29/66 ,  H01L29/161 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract translation: 半导体结构包括第一应变翅片部分和第二应变翅片部分，在相应的应变翅片部分上的一对无效内部门结构，以及在非活性内部门结构的外侧壁表面上的间隔物， 内门结构，以及在第一应变翅片部分和第二应变翅片部分端表面上。 第一应变翅片部分和第二应变翅片部分端面与非活性内部门结构的相应的内侧壁表面共面。 形成在端面上的间隔限制了第一应变翅片部分和第二应变翅片部分的松弛，并且限制了第一应变翅片部分和第二应变翅片部分之间的短路。

公开(公告)号：US09570299B1

公开(公告)日：2017-02-14

申请号：US14847619

申请日：2015-09-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Juntao Li

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/06 ,  H01L29/161 ,  G01N33/00 ,  B82Y15/00 ,  B82Y40/00

CPC classification number: H01L21/02694 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01N33/0036 ,  G01N33/005 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02606 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  Y10S977/814 ,  Y10S977/89 ,  Y10S977/90 ,  Y10S977/957

Abstract: Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

Abstract translation: 提供了形成纳米结构材料的技术。 在本发明的一个方面，一种用于在埋层绝缘体上形成纳米管的方法包括以下步骤：在SOI晶片的SOI层中形成一个或多个翅片，其中SOI晶片具有通过埋置的SOI层与SOI层分离的衬底 绝缘子; 在翅片上形成SiGe层; 在足以从SiGe层驱入Ge到翅片中的条件下退火SiGe层，并形成完全围绕每个翅片的SiGe壳; 并且去除对SiGe壳体有选择性的散热片，其中剩余的SiGe壳体在埋入的绝缘体上形成纳米管。 还提供了纳米管结构和形成纳米管器件的方法。

公开(公告)号：US20170018465A1

公开(公告)日：2017-01-19

申请号：US15220150

申请日：2016-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/02 ,  H01L29/161 ,  H01L21/306 ,  H01L21/324 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

Abstract: A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

Abstract translation: 用于形成翅片的方法包括在体Si衬底的表面上生长SiGe层和硅层，从硅层和SiGe层图案化翅片结构，并用电介质填充物填充翅片结构。 形成沟槽以暴露翅片结构的端部。 翅片结构的第一个区域被阻挡。 通过从端部选择性地蚀刻翅片结构来去除第二区域的翅片结构的SiGe层，以形成填充有电介质材料的空隙。 翅片结构的硅层被暴露。 第一区域中的SiGe层被热氧化以将Ge驱动到硅层中，以在第一区域中的氧化物层上形成SiGe散热片，并在第二区域中在介电材料上形成硅散热片。