公开(公告)号：US20170005180A1

公开(公告)日：2017-01-05

申请号：US14754751

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

公开(公告)号：US20160293610A1

公开(公告)日：2016-10-06

申请号：US14672282

申请日：2015-03-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1108 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/413 ,  H01L29/66545

Abstract: A semiconductor device including a pFET and an nFET where: (i) the gate and conductor channel of the pFET are electrically insulated from a buried oxide layer; and (ii) the conductor channel of the nFET is in the form of a fin extending upwards from, and in electrical contact with, the buried oxide layer. Also, a method of making the pFET by adding a fin structure extending from the top surface of the buried oxide layer, then condensing germanium locally into the lattice structure of the lower portion of the fin structure, and then etching away the lower portion of the fin structure so that it becomes a carrier channel suspended above, and electrically insulated from the buried oxide layer.

Abstract translation: 一种包括pFET和nFET的半导体器件，其中：（i）pFET的栅极和导体沟道与掩埋氧化物层电绝缘; 和（ii）nFET的导体通道为从掩埋氧化物层向上延伸并与之相接触的翅片的形式。 此外，通过添加从掩埋氧化物层的顶面延伸的翅片结构，然后将锗局部冷凝到翅片结构的下部的晶格结构中，然后蚀刻除去栅极结构的下部，从而制造pFET的方法 翅片结构，使其成为悬挂在上面并与掩埋氧化物层电绝缘的载流子通道。

公开(公告)号：US20160211328A1

公开(公告)日：2016-07-21

申请号：US15076880

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/161 ,  H01L27/12

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

Abstract translation: 访问具有nFET和pFET区域的硅锗绝缘体（SGOI）晶片，SGOI晶片具有具有第一锗（Ge）浓度的硅锗（SiGe）层，以及nFET和pFET上的第一氧化物层，并且去除第一 pFET上的氧化层。 然后，将pFET中的SiGe层中的第一Ge浓度提高到第二Ge浓度，并且去除nFET上的第一氧化物层。 然后，使nFET中的第一Ge浓度的SiGe层凹陷，使得SiGe层与第二Ge浓度的pFET中的SiGe层成平面。 然后，在nFET中的SGOI上生长硅（Si）层，并且在pFET中生长第三浓度的SiGe层，其中第三浓度的SiGe层与生长的nFET Si层成平面。

公开(公告)号：US09263550B2

公开(公告)日：2016-02-16

申请号：US14255440

申请日：2014-04-17

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/763 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/7624 ,  H01L21/763 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: A method of fabricating a device is provided which includes selectively implanting one or more dopants into a semiconductor wafer so as to form doped and undoped regions of the wafer; forming fins in the wafer with at least a given one of the fins being formed both from a portion of the doped region of the wafer and from a portion of the undoped region of the wafer; forming dummy gates on the wafer; depositing a filler layer around the dummy gates; removing the dummy gates forming trenches in the filler layer, at least one of which extends down to the undoped portion of the fin and at least another of which extends down to the doped portion of the fin; selectively forming a gate dielectric lining the trenches which extend down to the undoped portion of the fin; and forming replacement gates in the trenches.

Abstract translation: 提供一种制造器件的方法，其包括将一个或多个掺杂剂选择性地注入到半导体晶片中，以形成晶片的掺杂和未掺杂区域; 在晶片中形成翅片，其中至少一个翅片由晶片的掺杂区域的一部分和晶片的未掺杂区域的一部分形成; 在晶片上形成伪栅极; 在虚拟门周围沉积填充层; 去除在填充层中形成沟槽的虚拟栅极，其中至少一个向下延伸到鳍片的未掺杂部分，并且至少另一个延伸到鳍片的掺杂部分; 选择性地形成向下延伸到翅片的未掺杂部分的沟槽的栅极电介质; 并在沟槽中形成替换门。

公开(公告)号：US20150303262A1

公开(公告)日：2015-10-22

申请号：US14511837

申请日：2014-10-10

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/06 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

公开(公告)号：US20150287642A1

公开(公告)日：2015-10-08

申请号：US14245627

申请日：2014-04-04

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/24 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

公开(公告)号：US20150179781A1

公开(公告)日：2015-06-25

申请号：US14135668

申请日：2013-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

Abstract translation: 在绝缘体层上形成由一对半导体焊盘部分横向邻接的至少一个半导体纳米线。 从至少一个半导体纳米线下方蚀刻绝缘体层的一部分，使得至少一个半导体纳米线被悬浮。 临时填充材料沉积在至少一个半导体纳米线上，并且被平坦化以物理地暴露该对半导体焊盘部分的顶表面。 沟槽形成在该对半导体焊盘部分内，并且填充有应力产生材料。 随后取出临时填充材料。 所述至少一个半导体纳米线在拉伸应变或压缩应变下沿长度方向应变。

公开(公告)号：US09029213B2

公开(公告)日：2015-05-12

申请号：US13891873

申请日：2013-05-10

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey N. Sleight

IPC: H01L21/77 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

Abstract translation: 在绝缘体层上形成至少一个半导体鳍片。 绝缘体层的一部分从至少一个半导体鳍片的下方蚀刻。 选择绝缘体的蚀刻部分的量使得金属栅极电极层填充绝缘体层的凹陷表面与至少一个半导体鳍片的底表面之间的整个间隙。 金属栅极电极层和半导体栅极电极层之间的界面在该至少一个半导体鳍片上连续地延伸，并且不在至少一个半导体鳍片的任何一个之下。 在栅电极的图形化期间，由于半导体栅极电极层不存在于至少一个半导体鳍片之下，所以能够促进半导体栅极电极层中的半导体材料的去除。

公开(公告)号：US08994108B2

公开(公告)日：2015-03-31

申请号：US13971974

申请日：2013-08-21

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  B82Y99/00

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66136 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/938

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

公开(公告)号：US08927431B2

公开(公告)日：2015-01-06

申请号：US13906392

申请日：2013-05-31

Applicant: International Business Machines Corporation

Inventor： Stephen W. Bedell ,  Gen P. Lauer ,  Isaac Lauer ,  Joseph S. Newbury

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3065

Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

Abstract translation: 提供了使用化学气相蚀刻工艺以高速度蚀刻硅衬底的方法。 可以通过在处理室中加热硅衬底然后将盐酸和含锗化合物流入处理室来蚀刻硅衬底。 衬底可以被加热到至少700℃。盐酸流速可以是至少约100（标准立方厘米每分钟）sccm。 在一些实施方案中，盐酸流速可以在约10slm至约20标准升/分钟（slm）之间。 携带锗的化合物流速可以至少为约50sccm。 在一些实施方案中，携带锗的化合物流速可以在约100sccm至约500sccm之间。 蚀刻可以完全延伸穿过硅衬底。