公开(公告)号：US11231985B1

公开(公告)日：2022-01-25

申请号：US16935123

申请日：2020-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anupama Jagannathan ,  Karthick Rajamani ,  Han Na ,  Amos A. Omokpo

IPC: G06F11/07 ,  G06N20/00

Abstract: A system is configured to determine a dominant error causing a provisioning step to become stuck during provisioning of a machine in a cloud environment. The system includes memory for storing instructions, and a processor configured to execute said instructions to determine an inverse error frequency (IEF) value for pre-intervention errors in a set of intervention provisioning data; determine a dominant error for a provision during said provisioning step in said set of intervention provisioning data based on a pre-intervention error that has a maximum IEF value; determine a duration frequency (DuF) value for the provision at said provisioning step for provisions in a set of non-intervention provisioning data; and determine said dominant error for each provision during said provisioning step in said set of non-intervention provisioning data based on an error that resulted in DuF value.

公开(公告)号：US11029739B2

公开(公告)日：2021-06-08

申请号：US16688110

申请日：2019-11-19

Applicant: International Business Machines Corporation

Inventor： Malcolm S. Allen-Ware ,  Kanak B. Agarwal ,  Charles Lefurgy ,  Guillermo J. Silva ,  Thomas W. Keller ,  Karthick Rajamani ,  Yang Li ,  Ramakrishnan Rajamony

IPC: G06F1/26 ,  G05B15/02 ,  G06F1/3296 ,  G06F1/3209 ,  G06F1/3228 ,  G06F1/3203 ,  G06F1/3215 ,  G06F1/3206 ,  G06F1/32 ,  H02J13/00

Abstract: A computer controls power distribution. The computing system determines a power budget for a portion of a topography for a power delivery system. The computing system generates a pool of worker programs for the portion of the topography. The computing system generates a first number of power management tasks to manage power consumption in the portion of the topography based on the power budget. The computing system sends the first number of power management tasks to at least one worker program included in the pool of worker programs.

公开(公告)号：US10283212B2

公开(公告)日：2019-05-07

申请号：US15362935

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Janani Mukundan ,  Karthick Rajamani ,  Saravanan Sethuraman

IPC: G11C29/12 ,  G11C29/50 ,  G11C29/52 ,  G11C14/00 ,  G11C11/16 ,  G11C29/04

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

公开(公告)号：US20190095235A1

公开(公告)日：2019-03-28

申请号：US15712194

申请日：2017-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wesley M. Felter ,  Junaid Khalid ,  Karthick Rajamani ,  Eric Rozner ,  Cong Xu

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/46 ,  G06F9/4818 ,  H04L67/10 ,  H04L67/325

Abstract: Utilizing a computing device to determine and enforce limits on cloud computing containers transmitting data over a network. A determination is made of total container time remaining available for a first container to execute in a computing environment, the first container utilizing one or more processor threads executing on a computing device. Processor packet transmission time is determined for processing and transmission of a packet or a batch of packets via a network stack associated with the computing device by the one or more processor threads utilized by the first container. An updated total container time remaining for the first container is calculated, accounting for the processor packet transmission time. The updated total container time remaining is enforced by descheduling all processor threads utilized by the first container if the updated total container time remaining is insufficient.

公开(公告)号：US10234927B2

公开(公告)日：2019-03-19

申请号：US14939111

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Malcolm S. Allen-Ware ,  Shawn P. Authement ,  John C. Elliott ,  Charles R. Lefurgy ,  J. Carlos A. Pratt ,  Karthick Rajamani ,  David B. Whitworth

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3221 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3206 ,  G06F3/06

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

公开(公告)号：US20180260330A1

公开(公告)日：2018-09-13

申请号：US15457801

申请日：2017-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wesley M. Felter ,  Alexandre P. Ferreira ,  Karthick Rajamani ,  Juan C. Rubio ,  Cong Xu

IPC: G06F12/0871 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F9/50 ,  G06F12/0842 ,  G06F2212/604

Abstract: Dynamically allocating cache in a multi-tenant infrastructure includes monitoring cache usage for multiple workloads in a multi-tenant processing infrastructure to determine a workload phase. A baseline performance level per workload is determined. The baseline performance level is dependent upon the workload phase. The workloads for each tenant are categorized based on cache utilization and the cache is allocated to each workload based on the baseline performance level, cache utilization, and system wide cache capacity.

公开(公告)号：US09811150B2

公开(公告)日：2017-11-07

申请号：US14937290

申请日：2015-11-10

Applicant: International Business Machines Corporation

Inventor： Malcolm S. Allen-Ware ,  Alan James Drake ,  Michael Stephen Floyd ,  Charles Robert Lefurgy ,  Karthick Rajamani ,  Tobias Webel

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F9/4418 ,  Y02D10/171

Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.

公开(公告)号：US09665346B2

公开(公告)日：2017-05-30

申请号：US14525313

申请日：2014-10-28

Applicant: International Business Machines Corporation

Inventor： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC: G06F7/38 ,  G06F7/483

CPC classification number: G06F7/483 ,  G06F2207/382

Abstract: Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

公开(公告)号：US20170139460A1

公开(公告)日：2017-05-18

申请号：US14939111

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Malcolm S. Allen-Ware ,  Shawn P. Authement ,  John C. Elliott ,  Charles R. Lefurgy ,  J. Carlos A. Pratt ,  Karthick Rajamani ,  David B. Whitworth

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3221 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

公开(公告)号：US09652356B2

公开(公告)日：2017-05-16

申请号：US14723989

申请日：2015-05-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heather L. Hanson ,  Venkat R. Indukuru ,  Francis P. O'Connell ,  Karthick Rajamani

IPC: G06F1/32 ,  G06F1/00 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/3024 ,  G06F11/3423 ,  Y02D10/126 ,  Y02D10/152

Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.