公开(公告)号：US09397002B1

公开(公告)日：2016-07-19

申请号：US14947081

申请日：2015-11-20

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/324

CPC classification number: H01L27/0886 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin pitch. Each of the fins has an undoped fin channel and a punchthrough stop doping region underneath the undoped fin channel. A narrow shallow trench isolation trench is formed between the fin pitch of the fins. A wide shallow trench isolation trench is formed at an outside edge of the fins. A doped layer fills the narrow shallow trench isolation trench and the wide shallow trench isolation trench. A vertical thickness of the doped layer in the narrow shallow trench isolation trench is greater than a vertical thickness of the wide shallow trench isolation trench.

Abstract translation: 一种技术涉及体散射场效应晶体管中的穿通停止（PTS）掺杂。 翅片形成在基板上，每对翼片具有翅片间距。 每个翅片具有未掺杂的翅片通道和在未掺杂的翅片通道下方的穿通停止掺杂区域。 在翅片的翅片间距之间形成窄的浅沟槽隔离沟槽。 在鳍片的外边缘处形成宽的浅沟槽隔离沟槽。 掺杂层填充窄的浅沟槽隔离沟槽和宽的浅沟槽隔离沟槽。 狭窄的浅沟槽隔离沟槽中的掺杂层的垂直厚度大于宽浅沟槽隔离沟槽的垂直厚度。

公开(公告)号：US20240194670A1

公开(公告)日：2024-06-13

申请号：US18078245

申请日：2022-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Fee Li Lie ,  Michael P. Belyansky ,  Matt Malley

IPC: H01L27/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32145 ,  H01L2224/83896

Abstract: A multi-layer stacked semiconductor device includes a first integrated circuit device and a bonding insulator layer formed upon the first integrated circuit device. The bonding insulator layer includes an insulating material layer and an etch stop layer. The semiconductor device also includes a second integrated circuit device formed over the first integrated circuit device in a stacked configuration. The semiconductor device also includes a bonding insulator layer formed between the second integrated circuit device and the insulating material layer. The insulating material layer and the bonding insulator layer are bonded adjacent to one another.

公开(公告)号：US11908723B2

公开(公告)日：2024-02-20

申请号：US17541946

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Akihiro Horibe ,  Qianwen Chen ,  Risa Miyazawa ,  Michael P. Belyansky ,  John Knickerbocker ,  Takashi Hisada

IPC: H01L21/68 ,  H01L21/683

CPC classification number: H01L21/681 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

公开(公告)号：US20230197721A1

公开(公告)日：2023-06-22

申请号：US17553967

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael P. Belyansky ,  Dechao Guo ,  Junli Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/04 ,  H01L23/00

CPC classification number: H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/785 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/045 ,  H01L24/83 ,  H01L2224/83896

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures that leverage wafer bonding techniques to provide stacked field effect transistors (SFETs) with high-quality N/P junction isolation. In a non-limiting embodiment of the invention, a first semiconductor structure is formed on a first wafer and a second semiconductor structure is formed on a second wafer. The first wafer is positioned with respect to the second wafer such that a top surface of the first semiconductor structure is directly facing a top surface of the second semiconductor structure. A bonding layer is formed between the top surface of the first semiconductor structure and the top surface of the second semiconductor structure and the first wafer is bonded to the second wafer at a first temperature. The device is annealed at a second temperature to cure the bonding layer. The anneal temperature is greater than the bonding temperature.

公开(公告)号：US11011624B2

公开(公告)日：2021-05-18

申请号：US16505411

申请日：2019-07-08

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/786

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

公开(公告)号：US10943992B2

公开(公告)日：2021-03-09

申请号：US16407564

申请日：2019-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Christopher J. Waskiewicz ,  Michael P. Belyansky ,  Brent Alan Anderson ,  Muthumanickam Sankarapandian ,  Puneet Suvarna ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L29/417 ,  H01L21/311

Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.

公开(公告)号：US20200243526A1

公开(公告)日：2020-07-30

申请号：US16847350

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US20200243525A1

公开(公告)日：2020-07-30

申请号：US16847122

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US10586700B2

公开(公告)日：2020-03-10

申请号：US15815111

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Richard A. Conti ,  Dechao Guo ,  Devendra K. Sadana ,  Jay W. Strane

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/3105 ,  H01L29/78

Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

公开(公告)号：US20200006137A1

公开(公告)日：2020-01-02

申请号：US16020412

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Marc Bergendahl ,  Victor W. C. Chan ,  JEFFREY C. SHEARER

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.