公开(公告)号：US20230180485A1

公开(公告)日：2023-06-08

申请号：US17540389

申请日：2021-12-02

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Steven Michael McDermott ,  Nicole Saulnier ,  Muthumanickam Sankarapandian ,  Injo Ok

IPC: H01L27/24 ,  H01L27/22 ,  H01L49/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/224 ,  H01L28/92 ,  H01L43/08 ,  H01L43/12 ,  H01L45/06 ,  H01L45/126 ,  H01L45/1675

Abstract: A two-terminal device comprises a bottom electrode. A device element is formed upon the bottom electrode. The two-terminal device also comprises a top electrode that is formed upon the device element. The bottom electrode and the top electrode are aligned. The bottom electrode and top electrode also have a same width and depth.

公开(公告)号：US20230114163A1

公开(公告)日：2023-04-13

申请号：US17485765

申请日：2021-09-27

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Chi-Chun Liu ,  Robin Hsin Kuo Chao ,  Muthumanickam Sankarapandian

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

公开(公告)号：US11302797B2

公开(公告)日：2022-04-12

申请号：US16799237

申请日：2020-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Thamarai S. Devarajan ,  Balasubramanian Pranatharthiharan ,  Sanjay C. Mehta ,  Muthumanickam Sankarapandian

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

公开(公告)号：US20210351073A1

公开(公告)日：2021-11-11

申请号：US16867757

申请日：2020-05-06

Applicant: International Business Machines Corporation

Inventor： Jennifer Fullam ,  Su Chen Fan ,  Christopher J. Waskiewicz ,  Muthumanickam Sankarapandian

IPC: H01L21/768

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

公开(公告)号：US20200066575A1

公开(公告)日：2020-02-27

申请号：US16112286

申请日：2018-08-24

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Muthumanickam Sankarapandian

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: Techniques for single trench damascene interconnect formation using TiN HMO are provided. In one aspect, a method for forming interconnects on a substrate includes: forming an underlayer on the substrate; forming a hardmask on the underlayer; patterning trenches in the hardmask that extend down to the underlayer; forming the interconnects in the trenches; removing the hardmask; and burying the interconnects in an ILD. The trenches can be patterned in the hardmask using a process such as sidewall image transfer. An interconnect structure is also provided.

公开(公告)号：US20200066519A1

公开(公告)日：2020-02-27

申请号：US16671686

申请日：2019-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Muthumanickam Sankarapandian ,  Soon-Cheon Seo ,  Indira P. Seshadri ,  John R. Sporre

IPC: H01L21/033 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311

Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

公开(公告)号：US20190385913A1

公开(公告)日：2019-12-19

申请号：US16557195

申请日：2019-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  Lam Research Corporation

Inventor： Georges Jacobi ,  Vimal K. Kamineni ,  Randolph F. Knarr ,  Balasubramanian Pranatharthiharan ,  Muthumanickam Sankarapandian

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28

Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.

公开(公告)号：US10256161B2

公开(公告)日：2019-04-09

申请号：US15045778

申请日：2016-02-17

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Muthumanickam Sankarapandian ,  Koji Watanabe

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/51

Abstract: A method for forming a semiconductor device includes forming a first channel region and a second channel region on a substrate, depositing a dielectric material layer on the first channel region and the second channel region, and depositing a barrier layer on the dielectric material layer on the first channel region and the second channel region. A metal layer is deposited on the barrier layer on the first channel region and the second channel region. A portion of the metal layer and the barrier layer on the first channel region and a portion of the metal layer on the second channel region are removed to expose the barrier layer on the second channel region. A layer of workfunction material is deposited on an exposed portion of the dielectric material layer on the first channel region and over the barrier layer on the second channel region.

公开(公告)号：US10242920B2

公开(公告)日：2019-03-26

申请号：US16023687

申请日：2018-06-29

Applicant: International Business Machines Corporation

Inventor： Michael A. Guillorn ,  Nicolas J. Loubet ,  Muthumanickam Sankarapandian

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L27/092 ,  H01L29/423

Abstract: Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide.

公开(公告)号：US20150275376A1

公开(公告)日：2015-10-01

申请号：US14736698

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： John A. Fitzsimmons ,  David L. Rath ,  Muthumanickam Sankarapandian

IPC: C23F1/40 ,  C23F1/02 ,  C09K13/00

CPC classification number: C23F1/40 ,  C09K13/00 ,  C23F1/02 ,  C23F1/32 ,  C23G1/205 ,  H01L21/283 ,  H01L21/32134 ,  H01L21/823842

Abstract: A chemical solution including an aqueous solution, an oxidizing agent, and a pH stabilizer selected from quaternary ammonium salts and quaternary ammonium alkali can be employed to remove metallic materials in cavities for forming a semiconductor device. For example, metallic materials in gate cavities for forming a replacement gate structure can be removed by the chemical solution of the present disclosure with, or without, selectivity among multiple metallic materials such as work function materials. The chemical solution of the present disclosure provides different selectivity among metallic materials than known etchants in the art.

Abstract translation: 可以使用包含水溶液，氧化剂和选自季铵盐和季铵碱的pH稳定剂的化学溶液来除去用于形成半导体器件的空腔中的金属材料。 例如，用于形成替代栅极结构的栅极腔中的金属材料可以通过本发明的化学溶液被去除，或者在多种金属材料如功函数材料中具有或不具有选择性。 本公开的化学溶液在金属材料中提供与本领域中已知的蚀刻剂不同的选择性。