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    HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS
    22.
    发明申请
    HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS 有权
    高K和P型工作功能金属第一制造工艺具有改进的退火工艺流程

    公开(公告)号：US20170025526A1

    公开(公告)日：2017-01-26

    申请号：US15183390

    申请日：2016-06-15

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

    IPC: H01L29/78 ,  H01L21/324 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

    Abstract translation: 实施例涉及一种形成鳍型场效应晶体管（FinFET）的部分的方法。 该方法包括形成至少一个翅片，并且在至少一个翅片的至少一部分上形成电介质层。 该方法还包括在电介质层的至少一部分上形成功函数层。 所述方法还包括形成与所述至少一个鳍片相邻的源极区域或漏极区域，以及执行退火操作，其中所述退火操作使所述电介质层和所述源极区域或所述漏极区域退火，并且其中所述功函数层提供 在退火操作期间到介电层的至少一部分的保护功能。

    TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
    26.
    发明申请
    TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS 有权
    使用多模式图像处理的测试方法

    公开(公告)号：US20150140697A1

    公开(公告)日：2015-05-21

    申请号：US14607160

    申请日：2015-01-28

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

    IPC: H01L21/66 ,  H01L21/8234

    CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

    Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

    Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

    TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS
    29.
    发明申请
    TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS 审中-公开
    用于监测深层隔离区域和局部分离区域的尺寸的测试结构

    公开(公告)号：US20170005014A1

    公开(公告)日：2017-01-05

    申请号：US14789476

    申请日：2015-07-01

    Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

    Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

    IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L22/32 ,  H01L21/76895 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

    Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

    Abstract translation: 实施例涉及一种方法。实施例涉及鳍式场效应晶体管（FinFET）的测试结构。 测试结构包括电耦合到FinFET的伪栅极的第一导电层和电耦合到FinFET的衬底的第二导电层。 测试结构还包括电耦合到FinFET的伪栅极的第三导电层，以及至少部分地由第一导电层和第二导电层限制的FinFET的第一区域。 所述测试结构还包括至少部分地由所述第二导电层和所述第三导电层限制的所述FinFET的第二区域，其中所述第一区域包括具有第一尺寸的第一电介质，并且其中所述第二区域包括具有 第二维度大于第一维度。

    Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
    30.
    发明授权
    Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods 有权
    具有自对准接触工艺流程和制造方法中线路电容降低的集成电路

    公开(公告)号：US09443944B2

    公开(公告)日：2016-09-13

    申请号：US14541754

    申请日：2014-11-14

    Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hui Zang ,  Balasubramanian Pranatharthiharan

    IPC: H01L29/417 ,  H01L29/40 ,  H01L21/28

    CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76801 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/401 ,  H01L29/785

    Abstract: Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region.

    Abstract translation: 提供了用于形成具有自对准接触工艺流程和制造中线路电容减小的半导体器件的器件和方法。 一种方法包括例如：获得具有至少一个源极，漏极和栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 以及在所述第一和第二接触区域上形成至少一个第一和第二小接触。 一个中间半导体器件包括例如：具有栅极，源极区和漏极区的晶片; 位于所述源的一部分上方的至少一个第一接触区域; 至少一个第二接触区域位于所述排水管的一部分上方; 位于所述第一接触区域上方的至少一个第一小接触件; 以及位于第二接触区域上方的至少一个第二小接触件。

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