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    Semiconductor memory device having metal-insulator transition film resistor
    23.
    发明授权
    Semiconductor memory device having metal-insulator transition film resistor 有权
    具有金属 - 绝缘体转移膜电阻器的半导体存储器件

    公开(公告)号：US07439566B2

    公开(公告)日：2008-10-21

    申请号：US11485340

    申请日：2006-07-13

    Applicant: Jae-Woong Hyun ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Choong-Rae Cho ,  Sung-Il Cho

    Inventor： Jae-Woong Hyun ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Choong-Rae Cho ,  Sung-Il Cho

    IPC: H01L29/06

    CPC classification number: H01L27/108 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/146

    Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

    Abstract translation: 半导体存储器件可以具有较低的漏电流和/或更高的可靠性，例如较长的保留时间和/或更短的刷新时间。 该装置可以包括开关装置和电容器。 开关器件的源极可以连接到金属 - 绝缘体转变膜电阻器的第一端，并且电容器的至少一个电极可以连接到金属 - 绝缘体转变膜电阻器的第二端。 金属 - 绝缘体转变膜电阻器可以根据提供给其第一和第二端的电压在绝缘体和导体之间转变。

    Transistor and method of operating transistor
    24.
    发明授权
    Transistor and method of operating transistor 失效
    晶体管及晶体管工作方式

    公开(公告)号：US07414295B2

    公开(公告)日：2008-08-19

    申请号：US11274475

    申请日：2005-11-16

    Applicant: Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    Inventor： Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    IPC: H01L29/8605 ,  G11C11/00

    CPC classification number: H01L29/685

    Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

    Abstract translation: 提供其通道的物理特性根据施加的电压而改变的晶体管，并且提供其制造和操作方法。 晶体管可以包括基板上的第一导电层，相继层叠在第一导电层上的相变层和第二导电层，形成在第二导电层上的第一电流方向限制单元和第二电流方向限制单元 通过在空间内分离，分别形成在第一电流方向限制单元和第二电流方向限制单元上的第三导电层和第四导电层，连接到第三导电层的字线，连接到第三导电层的位线 第四导电层和连接到字线的降压单元。

    Transistor, method of manufacturing transistor, and method of operating transistor
    25.
    发明申请
    Transistor, method of manufacturing transistor, and method of operating transistor 失效

    公开(公告)号：US20060108639A1

    公开(公告)日：2006-05-25

    申请号：US11274475

    申请日：2005-11-16

    Applicant: Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    Inventor： Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    IPC: H01L29/94 ,  H01L29/76

    CPC classification number: H01L29/685

    Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

    Method and apparatus for pyroelectric lithography using patterned emitter
    26.
    发明授权
    Method and apparatus for pyroelectric lithography using patterned emitter 失效
    使用图案化发射器的热电光刻的方法和装置

    公开(公告)号：US06566666B2

    公开(公告)日：2003-05-20

    申请号：US10230315

    申请日：2002-08-29

    Applicant: In-Kyeong Yoo

    Inventor： In-Kyeong Yoo

    IPC: H01J3700

    CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3175 ,  H01J2237/31777

    Abstract: A method and an apparatus for pyroelectric lithography using a patterned emitter is provided. In the apparatus for pyroelectric lithography, a pyroelectric emitter or a ferroelectric emitter is patterned using a mask and it is then heated. Upon heating, electrons are not emitted from that part of the emitter covered by the mask, but are emitted from the exposed part of the emitter not covered by the mask so that the shape of the emitter pattern is projected onto the substrate. To prevent dispersion of emitted electron beams, which are desired to be parallel, the electron beams are controlled using a magnet or a projection system, thereby achieving exact a one-to-one projection or a x-to-one projection of the desired pattern etched on the substrate.

    Abstract translation: 提供了一种使用图案化发射器进行热电光刻的方法和装置。 在用于热电光刻的装置中，使用掩模对热电发射体或铁电发射体进行图案化，然后将其加热。 在加热时，电子不会从掩模覆盖的发射体的那部分发射，而是从未被掩模覆盖的发射体的暴露部分发射，使得发射极图案的形状投影到基板上。 为了防止希望平行的发射电子束的分散，使用磁体或投影系统控制电子束，从而精确地实现所需图案的一对一投影或一对一投影 蚀刻在基板上。

    2T-1C ferroelectric random access memory and operation method thereof
    27.
    发明授权
    2T-1C ferroelectric random access memory and operation method thereof 有权
    2T-1C铁电随机存取存储器及其操作方法

    公开(公告)号：US06404667B1

    公开(公告)日：2002-06-11

    申请号：US09658942

    申请日：2000-09-11

    Applicant: In-Kyeong Yoo

    Inventor： In-Kyeong Yoo

    IPC: G11C1122

    CPC classification number: G11C11/22

    Abstract: A 2T-1C FRAM, each cell of which includes two transistors and one ferroelectric capacitor so that the “charging” and “discharging” of the ferroelectric capacitor used in conjunction with the p-n junction of the two transistors performs write/read operations without switching thereby avoiding degradation problems such as fatigue and imprint in the 2T-1C FRAM.

    Abstract translation: 一个2T-1C FRAM，每个单元包括两个晶体管和一个铁电电容器，使得与两个晶体管的pn结结合使用的铁电电容器的“充电”和“放电”执行写入/读取操作而不进行切换 避免2T-1C FRAM中的疲劳和压印等退化问题。

    Resistive RAM having at least one varistor and methods of operating the same
    29.
    发明授权
    Resistive RAM having at least one varistor and methods of operating the same 有权
    具有至少一个压敏电阻的电阻RAM及其操作方法

    公开(公告)号：US07714313B2

    公开(公告)日：2010-05-11

    申请号：US11655086

    申请日：2007-01-19

    Applicant: Jung-Hyun Lee ,  Eun-Hong Lee ,  Sang-Jun Choi ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    Inventor： Jung-Hyun Lee ,  Eun-Hong Lee ,  Sang-Jun Choi ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    IPC: H01L47/00

    CPC classification number: G11C13/003 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/76

    Abstract: Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.

    Abstract translation: 公开了具有至少一个压敏电阻的电阻式存储器件及其操作方法。 电阻式存储器件可以包括至少一个底部电极线，与至少一个底部电极线交叉的至少一个顶部电极线以及至少一个堆叠结构，该至少一个堆叠结构设置在至少一个顶部电极线和至少一个顶部电极线的交点处 一个底部电极线包括变阻器和数据存储层。

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