公开(公告)号：US20150294911A1

公开(公告)日：2015-10-15

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US20150235855A1

公开(公告)日：2015-08-20

申请号：US14701102

申请日：2015-04-30

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Juergen Foerster ,  Bernhard Weidgans ,  Norbert Urbansky ,  Tilo Rotth

IPC: H01L21/285 ,  C23C14/34 ,  H01L21/768

CPC classification number: H01L21/2855 ,  C23C14/14 ,  C23C14/34 ,  C23C14/3414 ,  C23C14/3492 ,  C23C14/54 ,  H01L21/76877

Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.

Abstract translation: 公开了各种技术，方法和装置，其中金属沉积在基板上，并且金属对基板引起的应力受到限制，例如限制晶片的弯曲。

公开(公告)号：US11776927B2

公开(公告)日：2023-10-03

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

CPC classification number: H01L24/29 ,  B23K35/262 ,  C22C13/02 ,  H01L24/83 ,  H01L2224/2922 ,  H01L2224/29211 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/29264 ,  H01L2224/29269 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US10700019B2

公开(公告)日：2020-06-30

申请号：US16418006

申请日：2019-05-21

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L23/58 ,  B81B7/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

公开(公告)号：US10134697B2

公开(公告)日：2018-11-20

申请号：US14995028

申请日：2016-01-13

Applicant: Infineon Technologies AG

Inventor： Dietrich Bonart ,  Ludger Borucki ,  Martina Debie ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.

公开(公告)号：US10090265B2

公开(公告)日：2018-10-02

申请号：US15191777

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Franziska Haering ,  Hans-Joachim Schulze ,  Bernhard Weidgans

IPC: H01L23/48 ,  H01L23/00 ,  H01L29/417 ,  H01L29/40 ,  H01L23/532 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.

公开(公告)号：US20170317042A1

公开(公告)日：2017-11-02

申请号：US15592941

申请日：2017-05-11

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US09362216B2

公开(公告)日：2016-06-07

申请号：US14737298

申请日：2015-06-11

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49575 ,  H01L23/147 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49822 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/42 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/37099

Abstract: In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

公开(公告)号：US09082626B2

公开(公告)日：2015-07-14

申请号：US13952080

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/147 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49822 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/42 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/37099

Abstract: In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Abstract translation: 在一个实施例中，器件包括设置在衬底上的第一导电焊盘以及设置在第一导电焊盘顶表面上的蚀刻停止层。 该器件还包括设置在蚀刻停止层上方的焊料阻挡层。

公开(公告)号：US20150028461A1

公开(公告)日：2015-01-29

申请号：US13952080

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/147 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49822 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/42 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/37099

Abstract: In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Abstract translation: 在一个实施例中，器件包括设置在衬底上的第一导电焊盘以及设置在第一导电焊盘顶表面上的蚀刻停止层。 该器件还包括设置在蚀刻停止层上方的焊料阻挡层。