公开(公告)号：US20190393356A1

公开(公告)日：2019-12-26

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Miriam RESHOTKO ,  Matthew METZ ,  Yih WANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Abhishek SHARMA ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L23/522 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304897A1

公开(公告)日：2019-10-03

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L27/108

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20190138893A1

公开(公告)日：2019-05-09

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20190042199A1

公开(公告)日：2019-02-07

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F7/544 ,  G11C8/10 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US20220310849A1

公开(公告)日：2022-09-29

申请号：US17840186

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Juan ALZATE VINASCO

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108 ,  H01L29/49

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098880A1

公开(公告)日：2020-03-26

申请号：US16142045

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Cory WEBER ,  Van H. LE ,  Sean MA

IPC: H01L29/47 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L27/24

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

公开(公告)号：US20230005921A1

公开(公告)日：2023-01-05

申请号：US17943038

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: H01L27/108 ,  G11C5/06

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

公开(公告)号：US20220308995A1

公开(公告)日：2022-09-29

申请号：US17214835

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Adrian C. MOGA ,  Abhishek SHARMA

IPC: G06F12/0802

Abstract: Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.

公开(公告)号：US20200098874A1

公开(公告)日：2020-03-26

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin WEBER ,  Harold KENNEL ,  Abhishek SHARMA ,  Christopher JEZEWSKI ,  Matthew V. METZ ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Van H. LE ,  Arnab SEN GUPTA

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L29/267 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L21/322

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066511A1

公开(公告)日：2020-02-27

申请号：US16113159

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Ilya KARPOV ,  Brian DOYLE ,  Prashant MAJHI ,  Abhishek SHARMA ,  Ravi PILLARISETTY

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/12 ,  C23C14/08 ,  C23C14/34 ,  C23C14/54

Abstract: Embodiments disclosed herein comprise a ferroelectric material layer and methods of forming such materials. In an embodiment, the ferroelectric material layer comprises hafnium oxide with an orthorhombic phase. In an embodiment, the ferroelectric material layer may also comprise trace elements of a working gas. Additional embodiments may comprise: a semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, a gate electrode over the semiconductor channel, and a gate dielectric between the gate electrode and the semiconductor channel. In an embodiment, the gate dielectric includes a ferroelectric hafnium oxide. In an embodiment, the hafnium oxide is substantially free from dopants.