公开(公告)号：US20210153351A1

公开(公告)日：2021-05-20

申请号：US17127829

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  Jeffrey KRIEGER

IPC: H05K1/11 ,  H01R12/52 ,  H05K5/02 ,  H05K1/18 ,  G11C5/06

Abstract: Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

公开(公告)号：US20210120670A1

公开(公告)日：2021-04-22

申请号：US17134028

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Guixiang TAN ,  Xiang LI ,  Casey WINKEL ,  George VERGIS

IPC: H05K1/11 ,  H05K5/02 ,  H05K5/00 ,  H05K7/20

Abstract: An apparatus is described. The apparatus includes a printed circuit board (PCB) dual in-line memory module (DIMM) connector having ejectors. The ejectors have a small enough vertical profile to permit unbent liquid cooling conduits to run across the DIMM's semiconductor chips.

公开(公告)号：US20180032429A1

公开(公告)日：2018-02-01

申请号：US15224134

申请日：2016-07-29

Applicant: Intel Corporation

Inventor： Min LIU ,  Zhenlin LUO ,  George VERGIS ,  Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Ross E. ZWISLER

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0871 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/023 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/202 ,  G06F2212/205 ,  G06F2212/222 ,  G06F2212/225 ,  G06F2212/271 ,  G06F2212/305 ,  G06F2212/604

Abstract: A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.

公开(公告)号：US20230017161A1

公开(公告)日：2023-01-19

申请号：US17950663

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/10 ,  G11C8/18

Abstract: System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

公开(公告)号：US20230007775A1

公开(公告)日：2023-01-05

申请号：US17871542

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H05K1/18 ,  H05K1/11

Abstract: Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.

公开(公告)号：US20220360002A1

公开(公告)日：2022-11-10

申请号：US17871611

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  Tongyan ZHAI ,  George VERGIS ,  Anthony M. CONSTANTINE ,  Jun LIAO

IPC: H01R12/72 ,  G06F1/18 ,  H01R13/24

Abstract: Methods and apparatus for differential I/O (input/output) cards using compression mount technology (CMT) connectors. Assemblies include a CMT connector having an array of spring-loaded pins or contacts that are configured to contact respective CMT contact pads on a pair of printed circuit board (PCBs), such as an add-in card (AIC) and a motherboard. Stacked assemblies are also disclosed including multiple CMT AIC or PCIe modules communicatively coupled using on module CMT connectors. The connector solutions may be used for AICs without changing the overall PCB form factor outline of existing AICs employing edge connectors. Under a stacked assembly of multiple CMT PCIe modules interconnected by on module CMT connectors, wiring in the PCBs is configured to provide signaling supporting multi-lane PCIe or CXL links for each CMT PCIe module. The CMT connector approach also is scalable and can support more pins/contacts to facilitate additional I/O bandwidth.

公开(公告)号：US20220300197A1

公开(公告)日：2022-09-22

申请号：US17749916

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G06F3/06

Abstract: Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.

公开(公告)号：US20220102917A1

公开(公告)日：2022-03-31

申请号：US17545947

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01R13/6471 ,  H05K5/02

Abstract: Examples described herein relate to a system that includes: a first device comprising a motherboard; a second device comprising a dual in-line memory module (DIMM); and an arrangement of a signal pin and ground pin pair coupled to the motherboard and DIMM wherein portions of the signal pin and ground pin pair are proximate each other.

公开(公告)号：US20210344130A1

公开(公告)日：2021-11-04

申请号：US17375558

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Xiang LI ,  Konika GANGULY ,  George VERGIS

IPC: H01R12/71 ,  H01R12/70

Abstract: A connector includes connector pins that have a loop of conductor. The connector connects a first printed circuit board (PCB) to a second PCB with compression of the connector pins between the two boards. In response to compression of the connector, the connector pins make electrical contact with themselves through the loop, while also connecting pads of the first PCB to pads of the second PCB.

公开(公告)号：US20210328370A1

公开(公告)日：2021-10-21

申请号：US17326148

申请日：2021-05-20

Applicant: Intel Corporation

Inventor： Phil GENG ,  Xiang LI ,  George VERGIS ,  Konika GANGULY

IPC: H01R12/70 ,  H01R43/26 ,  H05K1/02

Abstract: An apparatus is described. The apparatus includes a module having a connector along a center axis of the module. The module further includes a first set of semiconductor chips disposed in a first region of the module that resides between a first edge of the module and a first side of the connector, and, a second set of semiconductor chips disposed in a second region of the module that resides between a second opposite edge of the module and a second opposite side of the connector. A through hole does not exist between the first set of semiconductor chips and the first side of the connector nor between the second set of semiconductor chips and the second side of the connector. The module further includes a first through hole between a third edge of the connector and a third edge of the module and a second through hole between a fourth edge of the connector and a fourth edge of the module. The first and second through holes are to align with first and second studs that are to support a leaf spring when the leaf spring is bowed to press the connector into a printed circuit board.