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公开(公告)号：US11172581B2
公开(公告)日：2021-11-09
申请号：US16003970
申请日：2018-06-08
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Min Suet Lim , Tin Poay Chuah , Han Kung Chua
Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.
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公开(公告)号：US20210212205A1
公开(公告)日：2021-07-08
申请号：US17212016
申请日：2021-03-25
Applicant: Intel Corporation
Inventor： Khai Ern See , Jia Lin Liew , Tin Poay Chuah , Chee How Lim , Yi How Ooi
Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.
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公开(公告)号：US10856454B2
公开(公告)日：2020-12-01
申请号：US16535766
申请日：2019-08-08
Applicant: Intel Corporation
Inventor： Min Suet Lim , Yew San Lim , Jia Yan Go , Tin Poay Chuah , Eng Huat Goh
Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.
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公开(公告)号：US20190261504A1
公开(公告)日：2019-08-22
申请号：US16399825
申请日：2019-04-30
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Yew San Lim , Boon Ping Koh , Phaik Kiau Tan
Abstract: A folded circuit board includes a first circuit board and a second circuit board. The first circuit board and second circuit board are coupled together through a flexible interconnect. One or more folding guides are coupled to one of the first circuit board or second circuit board. The one or more folding guides extend beyond a first edge of the one of the first circuit board or second circuit board. The one or more folding guides include a curved sidewall configured to guide the flexible interconnect when the first circuit board is folded over the second circuit board. In one embodiment, the one or more folding guides are grounded to reduce EMI emissions.
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公开(公告)号：US20190008052A1
公开(公告)日：2019-01-03
申请号：US16003970
申请日：2018-06-08
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Min Suet Lim , Tin Poay Chuah , Han Kung Chua
Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.
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Patent Agency Ranking
公开(公告)号：US12218042B2
公开(公告)日：2025-02-04
申请号：US17204587
申请日：2021-03-17
Applicant: Intel Corporation
Inventor： Santosh Gangal , Tin Poay Chuah
Abstract: Disclosed herein are via plug resistors for incorporation into electronic substrates, and related methods and devices. Exemplary via plug resistor structures include a resistive element within and on a surface of a via extending at least partially through an electronic substrate and first and second electrodes coupled to the resistive element.
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公开(公告)号：US20240332127A1
公开(公告)日：2024-10-03
申请号：US18191242
申请日：2023-03-28
Applicant: Intel Corporation
Inventor： Eng Kwong Lee , Tin Poay Chuah , Chew Ching Lim
IPC: H01L23/38
CPC classification number: H01L23/38 , H10N10/17 , H10N10/8556
Abstract: In one embodiment, an integrated circuit package includes an integrated heat spreader (IHS) that incorporates a Peltier element. The IHS may include one or more Peltier elements, which may be in a top portion of the IHS. The Peltier element(s) may be electrically connected to the package substrate through a trace on a sidewall of the IHS.
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公开(公告)号：US11696409B2
公开(公告)日：2023-07-04
申请号：US16325659
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Min Suet Lim , Hoay Tien Teoh , Mooi Ling Chang , Chin Lee Kuan
CPC classification number: H05K1/184 , H05K1/111 , H05K1/113 , H05K1/16 , H05K1/162 , H05K1/165 , H05K1/167 , H05K1/183 , H05K2201/0305 , H05K2201/09072 , H05K2201/10454
Abstract: A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.
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公开(公告)号：US11589460B2
公开(公告)日：2023-02-21
申请号：US17090911
申请日：2020-11-06
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Min Suet Lim , Chee Chun Yee , Yew San Lim , Eng Huat Goh
Abstract: A multilayer printed circuit board including a first printed circuit board portion, including a first inserting connector, including a plurality of contacts for creating a first removable bus connection; a second printed circuit board portion, including a second inserting connector, including a plurality of contacts for creating a second removable bus connection; a third printed circuit board portion, connected between the first printed circuit board portion and to the second printed circuit board portion, wherein a rigidity of the third printed circuit board portion is less than a rigidity of each of the first printed circuit board portion and the second printed circuit board portion; wherein the multilayer printed circuit board is foldable along the third printed circuit board portion and, if so folded, the first printed circuit board portion is arranged on top of the second printed circuit board portion.
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公开(公告)号：US11487326B2
公开(公告)日：2022-11-01
申请号：US17088611
申请日：2020-11-04
Applicant: Intel Corporation
Inventor： Jeff Ku , Tin Poay Chuah , Yew San Lim , Min Suet Lim , Chee Chun Yee
Abstract: The present disclosure relates to a docking station including a triangular prism shaped body, and a cradle proximal to a top section of the triangular prism shaped body for detachably receiving a mobile device, wherein the cradle may include a plurality of different connection interfaces to provide a selectable connection with a complementary connection interface of the mobile device.
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