公开(公告)号：US20100173497A1

公开(公告)日：2010-07-08

申请号：US12655837

申请日：2010-01-06

申请人： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Seo-Woo Nam ,  In-Keun Lee ,  Jung-Hoon Lee

发明人： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Seo-Woo Nam ,  In-Keun Lee ,  Jung-Hoon Lee

IPC分类号： H01L21/306

CPC分类号： H01L21/32139

摘要： A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.

摘要翻译： 制造半导体集成电路器件的方法包括：提供衬底; 在基板上依次形成被蚀刻层，第一层和第二层; 在所述第一层和第二层上形成第一蚀刻掩模，所述第一蚀刻掩模具有以第一间距彼此分开并沿第一方向延伸的多个第一线图案; 使用第一蚀刻掩模在第二层和第一层上顺序地执行第一蚀刻以形成具有第二和第一图案的中间掩模图案; 在所述中间掩模图案上形成第二蚀刻掩模，所述第二蚀刻掩模包括以第二间距彼此分开并沿除了所述第一方向之外的第二方向延伸的多个第二线图案; 在第二图案的一部分上使用第二蚀刻掩模进行第二蚀刻，使得第二图案的剩余部分留在第一图案上; 在与第一图案上的第二蚀刻和中间掩模图案的第二图案的剩余部分不同的条件下，使用第二蚀刻掩模进行第三蚀刻，并形成最终的掩模图案; 并使用最终的掩模图案来图案化待蚀刻的层。

公开(公告)号：US07706159B2

公开(公告)日：2010-04-27

申请号：US11442451

申请日：2006-05-26

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G05F1/10

CPC分类号： H02M3/073

摘要： A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

摘要翻译： 用于DC-DC转换器的电荷泵包括接收输入电压的输入端子，输出输出电压的输出端子，串联连接在输入端子和输出端子之间的多个电荷泵浦级，以及电压电平转换器 第一和第二栅极时钟信号的电压电平，使得接收的第一和第二栅极时钟信号具有预定的幅度。 因此，电荷泵可以通过使VGS的幅度最大化来提高功率效率。 使用电荷泵的DC-DC转换器也可以应用于便携式设备，以最小化功耗，并且提供了一种用于提高DC-DC转换器的功率效率的方法。

公开(公告)号：US07635645B2

公开(公告)日：2009-12-22

申请号：US11028515

申请日：2005-01-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

摘要翻译： 公开了形成互连线和互连线结构的方法。 该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。 在层间绝缘层上形成氧化阻隔层。 在氧化阻挡层上形成氧化物覆盖层。 通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。 导电层图案形成在通孔内。

公开(公告)号：US20090167319A1

公开(公告)日：2009-07-02

申请号：US12344024

申请日：2008-12-24

申请人： Sun-Jung Lee ,  Hong-Jae Shin

发明人： Sun-Jung Lee ,  Hong-Jae Shin

IPC分类号： G01R31/28

CPC分类号： G01R31/31717 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008

摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

摘要翻译： 测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

公开(公告)号：US20090085075A1

公开(公告)日：2009-04-02

申请号：US12196454

申请日：2008-08-22

申请人： Ki-chul KIM ,  Hong-Jae Shin ,  Jung-Deog Lee

发明人： Ki-chul KIM ,  Hong-Jae Shin ,  Jung-Deog Lee

IPC分类号： H01L29/78 ,  H01L21/3205 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/28044 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： A method of fabricating a MOS transistor, and a MOS transistor fabricated by the method. The method can include forming a gate pattern on a semiconductor substrate. The gate pattern can be formed by sequentially stacking a gate electrode and a capping layer pattern. The capping layer pattern is formed to have a lower capping layer pattern and an upper capping layer pattern. The lower capping layer pattern is formed to a smaller width than the upper capping layer pattern.

摘要翻译： 一种制造MOS晶体管的方法和通过该方法制造的MOS晶体管。 该方法可以包括在半导体衬底上形成栅极图案。 栅极图案可以通过顺序堆叠栅电极和覆盖层图案来形成。 盖层图案形成为具有较低的封盖层图案和上覆盖层图案。 下盖层图案形成为比上盖层图案小的宽度。

公开(公告)号：US07417302B2

公开(公告)日：2008-08-26

申请号：US11174864

申请日：2005-07-05

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US20060290615A1

公开(公告)日：2006-12-28

申请号：US11453529

申请日：2006-06-15

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G09G3/30

CPC分类号： G09G3/3283 ,  G09G3/2014 ,  G09G3/3216 ,  G09G2320/0233

摘要： A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

摘要翻译： 一种显示装置，包括多个像素; 用于将数据信号输出到像素的数据驱动器; 偏置电流输出单元，用于输出具有预定大小的偏置电流; 多个驱动电流输出单元，用于向像素输出驱动电流; 以及第一开关，连接在所述偏置电流输出单元和所述驱动电流输出单元之间，用于选择所述驱动电流输出单元中的一个连接到所述偏置电流输出单元，其中所述驱动电流的大小基本上与 偏置电流。

公开(公告)号：US20060279352A1

公开(公告)日：2006-12-14

申请号：US11442451

申请日：2006-05-26

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G05F1/10 ,  H02M3/18

CPC分类号： H02M3/073

摘要： A charge pump for a DC-DC converter includes an input terminal receiving an input voltage, an output terminal outputting an output voltage, a plurality of charge pumping stages connected in series between the input terminal and the output terminal, and a voltage level shifter shifting voltage levels of first and second gate clock signals so that received first and second gate clock signals have a predetermined amplitude. Therefore, the charge pump can increase power efficiency by maximizing a magnitude of VGS. A DC-DC converter using the charge pump can also be applied to a portable device, for minimizing power consumption, and a method for improving power efficiency of the DC-DC converter is provided.

摘要翻译： 用于DC-DC转换器的电荷泵包括接收输入电压的输入端子，输出输出电压的输出端子，串联连接在输入端子和输出端子之间的多个电荷泵浦级，以及电压电平转换器 第一和第二栅极时钟信号的电压电平，使得接收的第一和第二栅极时钟信号具有预定的幅度。 因此，电荷泵可以通过使V GS的大小最大化来提高功率效率。 使用电荷泵的DC-DC转换器也可以应用于便携式设备，以最小化功耗，并且提供了一种用于提高DC-DC转换器的功率效率的方法。

公开(公告)号：US06936533B2

公开(公告)日：2005-08-30

申请号：US09994508

申请日：2001-11-27

申请人： Jae-Hak Kim ,  Hong-Jae Shin ,  Soo-Geun Lee ,  Kyoung-Woo Lee

发明人： Jae-Hak Kim ,  Hong-Jae Shin ,  Soo-Geun Lee ,  Kyoung-Woo Lee

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/58

CPC分类号： H01L21/76826 ,  H01L21/02126 ,  H01L21/02137 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3144 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

摘要翻译： 公开了一种制造具有低介电常数的半导体器件的方法。 根据该方法，形成碳氧化硅层，用等离子体处理并图案化。 碳硅氧化物层通过涂布法或CVD法如PECVD法形成。 用等离子体处理碳氧化硅层是通过供给至少一种选自He，H 2 H 2，N 2 O，NH 3， N 2，N 2，O 2和Ar。 希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。 在封盖层进一步堆叠和图案化的情况下，希望用H 2 - 等离子体处理。 即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

公开(公告)号：US08816944B2

公开(公告)日：2014-08-26

申请号：US11453529

申请日：2006-06-15

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G09G3/30

CPC分类号： G09G3/3283 ,  G09G3/2014 ,  G09G3/3216 ,  G09G2320/0233

摘要： A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

摘要翻译： 一种显示装置，包括多个像素; 用于将数据信号输出到像素的数据驱动器; 偏置电流输出单元，用于输出具有预定大小的偏置电流; 多个驱动电流输出单元，用于向像素输出驱动电流; 以及第一开关，连接在所述偏置电流输出单元和所述驱动电流输出单元之间，用于选择所述驱动电流输出单元中的一个连接到所述偏置电流输出单元，其中所述驱动电流的大小基本上与 偏置电流。