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公开(公告)号：US08502620B2
公开(公告)日：2013-08-06
申请号：US12944847
申请日：2010-11-12
Applicant: Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
Inventor： Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
CPC classification number: H01F21/12 , H01F27/2804 , H01F2027/2809 , H03H7/42 , Y10T29/49117
Abstract: A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers.
Abstract translation: 公开了一种用于发送信号的系统和方法。 一个实施例包括一个平衡 - 不平衡变换器，例如Marchand平衡 - 不平衡转换器，其具有带初级线圈的第一变压器和第一次级线圈，以及具有初级线圈的第二变压器和第二次级线圈。 第一次级线圈和第二次级线圈连接到接地平面，并且接地平面具有位于第一变压器和第二变压器中的线圈分离下方的槽线。 缝线也可以具有手指。
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公开(公告)号：US20120119845A1
公开(公告)日：2012-05-17
申请号：US12944847
申请日：2010-11-12
Applicant: Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
Inventor： Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
CPC classification number: H01F21/12 , H01F27/2804 , H01F2027/2809 , H03H7/42 , Y10T29/49117
Abstract: A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers.
Abstract translation: 公开了一种用于发送信号的系统和方法。 一个实施例包括一个平衡 - 不平衡变换器，例如Marchand平衡 - 不平衡转换器，其具有带初级线圈的第一变压器和第一次级线圈，以及具有初级线圈的第二变压器和第二次级线圈。 第一次级线圈和第二次级线圈连接到接地平面，并且接地平面具有位于第一变压器和第二变压器中的线圈分离下方的槽线。 缝线也可以具有手指。
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公开(公告)号：US20090195327A1
公开(公告)日：2009-08-06
申请号：US12023184
申请日：2008-01-31
Applicant: Shu-Ying Cho , Tzu-Jin Yeh , Sally Liu
Inventor： Shu-Ying Cho , Tzu-Jin Yeh , Sally Liu
IPC: H01P3/08
CPC classification number: H01P3/003 , H01P3/06 , H05K1/0219 , H05K1/0242 , H05K1/025 , H05K2201/09236 , H05K2201/09727 , H05K2201/09781
Abstract: A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis.
Abstract translation: 沿着信号线发送射频信号的半导体装置包括沿主轴延伸的信号线。 在信号线的一侧是第一电介质，信号线的相对侧是第二电介质。 第一和第二接地线分别靠近第一和第二电介质，并且接地线近似平行于信号线。 该装置具有沿主轴变化的横截面。
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公开(公告)号：US08797104B2
公开(公告)日：2014-08-05
申请号：US13445955
申请日：2012-04-13
Applicant: Hsieh-Hung Hsieh , Yi-Hsuan Liu , Chiao-Han Lee , Tzu-Jin Yeh , Chewn-Pu Jou
Inventor： Hsieh-Hung Hsieh , Yi-Hsuan Liu , Chiao-Han Lee , Tzu-Jin Yeh , Chewn-Pu Jou
IPC: H03F3/14
CPC classification number: H03F1/223 , H01L27/0727 , H03F3/193 , H03F2200/294 , H03F2200/318 , H03F2200/408 , H03F2200/411 , H03F2200/492
Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.
Abstract translation: 低噪声放大器包括具有被配置为接收振荡输入信号的栅极的第一晶体管和耦合到地的源极。 第二晶体管具有耦合到第一晶体管的漏极的源极，耦合到偏置电压的栅极和耦合到输出节点的漏极。 第一和第二晶体管中的至少一个包括耦合到隔离电路的浮动深n阱。
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公开(公告)号：US20120286888A1
公开(公告)日：2012-11-15
申请号：US13103592
申请日：2011-05-09
Applicant: Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
Inventor： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
CPC classification number: H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2201/0266
Abstract: A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.
Abstract translation: 一种系统包括压控振荡器，其包括电感器和可变电容器以及与可变电容器并联连接的开关电容器阵列。 开关电容器阵列还包括多个电容器组，其中使用温度计代码来控制每个电容器组。 此外，当开关电容器阵列由n位温度计代码控制时，开关电容器阵列为压控振荡器的振荡频率提供N个调谐步骤。
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Patent Agency Ranking
公开(公告)号：US20110265051A1
公开(公告)日：2011-10-27
申请号：US12766732
申请日：2010-04-23
Applicant: Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
Inventor： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
IPC: G06F17/50
CPC classification number: G06F17/5036 , G06F2217/82
Abstract: In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.
Abstract translation: 根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局 和仿真结果的模拟。 多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。
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公开(公告)号：US20090224791A1
公开(公告)日：2009-09-10
申请号：US12042606
申请日：2008-03-05
Applicant: Hsiao-Tsung Yen , Tzu-Jin Yeh , Sally Liu
Inventor： Hsiao-Tsung Yen , Tzu-Jin Yeh , Sally Liu
IPC: G01R31/27
CPC classification number: G01R31/2884 , H01L22/34
Abstract: A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).
Abstract translation: 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件（“DUT”）的固有特性的一组参数。
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公开(公告)号：US20070257339A1
公开(公告)日：2007-11-08
申请号：US11382202
申请日：2006-05-08
Applicant: Hsien-Wei Chen , Victor Chang , Tzu-Jin Yeh , Shu-Ying Cho , Keh-Jeng Chang , Kwang-Leei Young
Inventor： Hsien-Wei Chen , Victor Chang , Tzu-Jin Yeh , Shu-Ying Cho , Keh-Jeng Chang , Kwang-Leei Young
IPC: H01L23/62
CPC classification number: H01L23/552 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H05K1/0219 , H05K1/0298 , H05K2201/09236 , H05K2201/09618 , H01L2924/00
Abstract: Shield structures are provided. A first and second shield lines are formed over a substrate and coupled with a first voltage. A conductive line is formed between the first and the second shield lines, and coupled with a second voltage. The first shield layer is formed over the substrate and coupled to the first and the second shield lines via at least one first conductive structure.
Abstract translation: 提供盾构结构。 第一和第二屏蔽线形成在衬底上并与第一电压耦合。 在第一和第二屏蔽线之间形成导线，并与第二电压耦合。 第一屏蔽层形成在衬底上并且经由至少一个第一导电结构耦合到第一屏蔽线和第二屏蔽线。
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公开(公告)号：US09780211B2
公开(公告)日：2017-10-03
申请号：US13731873
申请日：2012-12-31
Applicant: Chewn-Pu Jou , Tzu-Jin Yeh , Chia-Chung Chen
Inventor： Chewn-Pu Jou , Tzu-Jin Yeh , Chia-Chung Chen
IPC: H01L27/088 , H01L29/78 , H01L29/66
CPC classification number: H01L29/785 , H01L29/66901
Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.
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公开(公告)号：US09129940B2
公开(公告)日：2015-09-08
申请号：US13419911
申请日：2012-03-14
Applicant: Hsieh-Hung Hsieh , Yi-Hsuan Liu , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
Inventor： Hsieh-Hung Hsieh , Yi-Hsuan Liu , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC: G01R35/00 , H01L23/48 , H01L23/66 , H01L25/065 , H04B5/00
CPC classification number: H01L23/48 , H01L23/66 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H04B5/0075 , H01L2924/00
Abstract: An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.
Abstract translation: 集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。 第一芯片包括射频电路和电耦合到射频电路的第一线圈。 第二芯片包括校准电路和电耦合到校准电路的第二线圈。 校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。
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