公开(公告)号：US08710108B2

公开(公告)日：2014-04-29

申请号：US13039470

申请日：2011-03-03

申请人： Keping Wang ,  Jing Li ,  Yunsong Yang

发明人： Keping Wang ,  Jing Li ,  Yunsong Yang

IPC分类号： C08J5/20 ,  B01J39/18 ,  C08J11/04 ,  H01M8/10 ,  H01M4/48

CPC分类号： C08J5/2256 ,  C08J2383/08

摘要： A proton conducting polymer electrolyte comprising a proton conducting ionomer cross-linked with an amount of a copolymer additive comprising cross-linking functional groups and other functional groups (e.g. proton carriers, chelating agents, radical scavengers) shows improved durability over the ionomer alone and provides for more stable inclusion of these other functional groups. The copolymer additive comprises at least two types of metal oxide monomers, one having cross-linking functional groups and the other having the other functional groups.

摘要翻译： 包含与包含交联官能团和其它官能团（例如质子载体，螯合剂，自由基清除剂）的共聚物添加剂交联的质子传导离聚物的质子传导性聚合物电解质显示出比单独的离聚物更好的耐久性，并提供 以更稳定地包含这些其它官能团。 共聚物添加剂包括至少两种类型的金属氧化物单体，一种具有交联官能团，另一种具有其它官能团。

公开(公告)号：US08687398B2

公开(公告)日：2014-04-01

申请号：US13407813

申请日：2012-02-29

申请人： Leland Chang ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

发明人： Leland Chang ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

公开(公告)号：US20140062527A1

公开(公告)日：2014-03-06

申请号：US13602905

申请日：2012-09-04

申请人： Michael Mills ,  Jing Li ,  Riad Samir Wahby

发明人： Michael Mills ,  Jing Li ,  Riad Samir Wahby

IPC分类号： H03K19/003

CPC分类号： H03K19/003

摘要： An isolation receiver includes at least one isolation capacitor to provide a first logic signal in response to a second logic signal that is provided by a transmitter. The receiver includes a signal processing circuit to amplify the first logic signal to generate an amplified signal, and the signal processing circuit includes a an amplifier to apply a nonlinear function. A comparator of the receiver provides a third logic signal in response to the amplified signal.

摘要翻译： 隔离接收器包括至少一个隔离电容器，以响应于由发射器提供的第二逻辑信号来提供第一逻辑信号。 接收机包括信号处理电路，用于放大第一逻辑信号以产生放大信号，并且信号处理电路包括一个放大器以应用非线性函数。 接收机的比较器响应于放大的信号提供第三逻辑信号。

公开(公告)号：US20140052900A1

公开(公告)日：2014-02-20

申请号：US13610830

申请日：2012-09-11

申请人： Bing Dai ,  Chung H. Lam ,  Jing Li

发明人： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F1/32 ,  G06F12/0246

摘要： A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

公开(公告)号：US08609228B2

公开(公告)日：2013-12-17

申请号：US12757091

申请日：2010-04-09

申请人： Yong Chen ,  Hongyu Chen ,  Xiao Bing Yun ,  Jing Li ,  Morgan M. Hughes ,  Rajen M. Patel

发明人： Yong Chen ,  Hongyu Chen ,  Xiao Bing Yun ,  Jing Li ,  Morgan M. Hughes ,  Rajen M. Patel

IPC分类号： B32B7/02

CPC分类号： B32B27/32 ,  B32B7/02 ,  B32B27/327 ,  B32B2250/03 ,  B32B2250/04 ,  B32B2250/05 ,  B32B2250/242 ,  B32B2307/31 ,  B32B2307/518 ,  B32B2439/70 ,  B32B2553/00 ,  Y10T428/24942 ,  Y10T428/265 ,  Y10T428/266 ,  Y10T428/2817 ,  Y10T428/31917 ,  Y10T428/31924 ,  Y10T428/31938

摘要： A multilayer biaxially oriented polypropylene film is disclosed which comprises at least three layers. The first layer is an outer layer comprising a first polymer which is a homopolymer polypropylene resin having a melting point of at least 155° C. The second layer is a core layer, having a melting point greater than 150° C. The core layer includes a blend comprising a second polymer which is a polypropylene homopolymer having a melting point of at least 155° C. and a third polymer having a melting point no greater than 145° C. The second polymer comprises from 20% to 80% by weight of the core layer while the third polymer comprises from 80% to 20% by weight of the core layer. The last required layer in the film is a sealant layer. The sealant layer comprises a fourth polymer having a melting point no greater than 145° C.

摘要翻译： 公开了一种包括至少三层的多层双轴取向聚丙烯薄膜。 第一层是包含第一聚合物的外层，第一聚合物是熔点至少为155℃的均聚聚丙烯树脂。第二层是熔点大于150℃的芯层。芯层包括 共混物，其包含第二聚合物，其是熔点为至少155℃的聚丙烯均聚物和熔点不大于145℃的第三聚合物。第二聚合物包含20重量％至80重量％ 核心层，而第三聚合物占芯层重量的80％至20％。 膜中最后需要的层是密封剂层。 密封层包括熔点不大于145℃的第四聚合物

公开(公告)号：US20130314983A1

公开(公告)日：2013-11-28

申请号：US13478932

申请日：2012-05-23

申请人： Chung H. Lam ,  Jing Li ,  Binquan Luan ,  Glenn J. Martyna ,  Dennis M. Newns

发明人： Chung H. Lam ,  Jing Li ,  Binquan Luan ,  Glenn J. Martyna ,  Dennis M. Newns

IPC分类号： G11C11/00 ,  H01L47/00

CPC分类号： G11C11/16 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.

公开(公告)号：US20130149235A1

公开(公告)日：2013-06-13

申请号：US13713490

申请日：2012-12-13

申请人： Baojian Shen ,  Jing Li ,  Xiaohua Wang ,  Wencheng Zhang ,  Qiaoxia Guo ,  Bojun Shen ,  Bing Feng ,  Guangming Wen ,  Zhihua Zhang ,  Ran Tian

发明人： Baojian Shen ,  Jing Li ,  Xiaohua Wang ,  Wencheng Zhang ,  Qiaoxia Guo ,  Bojun Shen ,  Bing Feng ,  Guangming Wen ,  Zhihua Zhang ,  Ran Tian

IPC分类号： B01J32/00

CPC分类号： C01B39/085 ,  B01J29/89 ,  B01J32/00 ,  B01J35/002

摘要： The present invention relates to a synthesis method for ETS-10 titanosilicate molecular sieves. The method comprises the steps of mixing a titanium oxide hydrosol, a silicon source, a sodium hydroxide, a fluorine-containing mineralizer and a water to give a gel and adjusting the pH thereof to 10.4 to 10.8; and hydrothermal crystallizing the gel at 170 to 250° C. for 10 to 100 hours to obtain the ETS-10 titanosilicate molecular sieves. In the synthesis method for ETS-10 titanosilicate molecular sieves provided by the present invention, a titanium oxide hydrosol is used as the titanium source to synthesize the ETS-10 titanosilicate molecular sieves, and the problem that conventional soluble titanium salt-based titanium sources tend to hydrolyze and the problem of poor dispersibility for the titanium source system of insoluble titanium oxide are therefore prevented. The ETS-10 titanosilicate molecular sieves synthesized has high purity and high crystallinity.

摘要翻译： 本发明涉及一种用于ETS-10钛硅酸盐分子筛的合成方法。 该方法包括以下步骤：将氧化钛水溶胶，硅源，氢氧化钠，含氟矿化剂和水混合，得到凝胶并将其pH调节至10.4至10.8; 并将该凝胶在170〜250℃水热结晶10〜100小时，得到ETS-10钛硅酸盐分子筛。 在本发明提供的ETS-10钛硅酸盐分子筛的合成方法中，使用钛氧化物水溶胶作为钛源来合成ETS-10钛硅酸盐分子筛，以及常规可溶性钛盐基钛源倾向于 从而可以防止水解不溶性氧化钛的钛源体系的分散性差的问题。 合成的ETS-10钛硅酸盐分子筛具有高纯度和高结晶度。

公开(公告)号：US20130135427A1

公开(公告)日：2013-05-30

申请号：US13307521

申请日：2011-11-30

申请人： Duanpei Wu ,  Jing Li ,  Shih-cheng Stan Yang ,  Herbert M. Wildfeuer ,  Anand Oswal

发明人： Duanpei Wu ,  Jing Li ,  Shih-cheng Stan Yang ,  Herbert M. Wildfeuer ,  Anand Oswal

IPC分类号： H04N7/15

CPC分类号： H04N7/15 ,  H04N21/23439 ,  H04N21/23655

摘要： A rate adaptive video conference bridge and related techniques are provided. At a video conference bridge, a source video stream is received from a source endpoint device in a network. The source video stream is encoded using a first encoder unit and second encoder unit to generate respective first and second encoded video streams. A determination is made whether to decrease or increase a bit rate of the source video stream based on network condition information. If the bit rate is to be decreased, the first encoder unit is instructed to send the first encoded video stream to a destination endpoint device. If the bit rate is to be increased, the second encoder unit is instructed to send the second encoded video stream to the destination endpoint device.

摘要翻译： 提供了速率自适应视频会议桥和相关技术。 在视频会议桥上，从网络中的源端点设备接收源视频流。 使用第一编码器单元和第二编码器单元对源视频流进行编码，以生成相应的第一和第二编码视频流。 根据网络条件信息确定是否减少或增加源视频流的比特率。 如果要降低比特率，则指示第一编码器单元将第一编码视频流发送到目的地端点设备。 如果要提高比特率，则指示第二编码器单元将第二编码视频流发送到目的地端点设备。

公开(公告)号：US20130039110A1

公开(公告)日：2013-02-14

申请号：US13209405

申请日：2011-08-14

申请人： Chung H. Lam ,  Jing Li ,  Kailash Gopalakrishnan

发明人： Chung H. Lam ,  Jing Li ,  Kailash Gopalakrishnan

IPC分类号： G11C5/02 ,  H01L21/02

CPC分类号： G11C13/00 ,  G11C5/02 ,  G11C7/00 ,  G11C11/16 ,  G11C11/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/71 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.

摘要翻译： 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。

公开(公告)号：US08370053B2

公开(公告)日：2013-02-05

申请号：US11945650

申请日：2007-11-27

申请人： Jing Li

发明人： Jing Li

IPC分类号： G08G1/00 ,  G08G1/123 ,  G06F19/00

CPC分类号： G08G1/01 ,  G08G1/096811 ,  G08G1/096838 ,  G08G1/096844

摘要： A method of method of assigning routes for a plurality of users allocated to different classes is provided. A first group of users is identified based on a user classification, wherein each user of the first group of users has a first user classification. A second group of users is identified based on the user classification, wherein each user of the second group of users has a second user classification. The first user classification is different from the second user classification. A disutility value is calculated for each user of the first group of users and for each user of the second group of users using a travel disutility function based on an origin and a destination of each user of the first group of users and each user of the second group of users. A bi-level problem solver is executed to optimize the disutility value based on the user classification. A route is recommended for each user of the first group of users and for each user of the second group of users based on the bi-level problem execution.

摘要翻译： 提供了一种为分配给不同类别的多个用户分配路由的方法的方法。 基于用户分类来识别第一组用户，其中第一组用户的每个用户具有第一用户分类。 基于用户分类来识别第二组用户，其中第二组用户的每个用户具有第二用户分类。 第一用户分类与第二用户分类不同。 对于第一组用户的每个用户以及基于第一组用户的每个用户的来源和目的地以及第一组用户的每个用户使用旅行不明性功能的第二组用户的每个用户计算不利值 第二组用户 执行双层问题求解器，以根据用户分类优化不利性值。 建议基于双层次问题执行的第一组用户的每个用户和第二组用户的每个用户的路由。