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    VERTICAL DEVICE WITH OPTIMAL TRENCH SHAPE
    22.
    发明申请
    VERTICAL DEVICE WITH OPTIMAL TRENCH SHAPE 失效
    具有最佳TRENCH形状的垂直装置

    公开(公告)号：US20050212027A1

    公开(公告)日：2005-09-29

    申请号：US10708861

    申请日：2004-03-29

    申请人： Thomas Adam ,  David Ahlgren ,  Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Thomas Adam ,  David Ahlgren ,  Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L29/945 ,  Y10S438/931

    摘要： A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the litho for the active area, in particular a DRAM cell with a vertical transistor.

    摘要翻译： 在半导体衬底中形成沟槽的方法包括将沟槽的上部的横截面从八边形转换为矩形的步骤，从而减小了沟槽光刻和有源区光刻之间对准误差的敏感性。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻层之间的未对准变得不敏感的垂直晶体管。

    Integration of fin-based devices and ETSOI devices
    25.
    发明授权
    Integration of fin-based devices and ETSOI devices 有权
    集成了鳍式设备和ETSOI设备

    公开(公告)号：US08779511B2

    公开(公告)日：2014-07-15

    申请号：US13530887

    申请日：2012-06-22

    申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L27/088

    CPC分类号： H01L27/1211 ,  H01L21/845

    摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

    摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

    METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES
    26.
    发明申请
    METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES 有权
    制备P-I-N二极体的方法，P-I-N二极体的结构和P-I-N二极体的设计结构

    公开(公告)号：US20100173449A1

    公开(公告)日：2010-07-08

    申请号：US12349018

    申请日：2009-01-06

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens ,  William Robert Tonti

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens ,  William Robert Tonti

    IPC分类号： H01L31/18 ,  G06F17/50 ,  H01L21/02

    CPC分类号： H01L29/868 ,  H01L29/6609

    摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.

    摘要翻译： 制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。 一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。

    Method of making a FinFET device structure having dual metal and high-k gates
    27.
    发明授权
    Method of making a FinFET device structure having dual metal and high-k gates 失效
    制造具有双金属和高k栅极的FinFET器件结构的方法

    公开(公告)号：US07736965B2

    公开(公告)日：2010-06-15

    申请号：US11951552

    申请日：2007-12-06

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L27/1211 ,  H01L29/517 ,  H01L29/66795

    摘要： Methods include making a FinFET device structure having multiple FinFET devices (e.g. ntype and/or ptype) with different metal conductors and/or different high-k insulators in the gates formed on a SOI substrate. One such method includes removing a second semiconductor layer from a second metal layer in a region above a second cap layer, from adjoining regions and from regions adjacent to a second fin.

    摘要翻译： 方法包括在SOI衬底上形成的栅极中制造具有多个FinFET器件（例如n型和/或p型）的FinFET器件结构，其具有不同的金属导体和/或不同的高k绝缘体。 一种这样的方法包括从邻接的区域和邻近第二鳍片的区域的第二盖层上方的区域中的第二金属层去除第二半导体层。

    Patterned strained semiconductor substrate and device
    28.
    发明授权
    Patterned strained semiconductor substrate and device 有权
    图形应变半导体衬底和器件

    公开(公告)号：US07682859B2

    公开(公告)日：2010-03-23

    申请号：US11931836

    申请日：2007-10-31

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L21/00

    CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

    摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

    摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

    METHOD OF MAKING A FINFET DEVICE STRUCTURE HAVING DUAL METAL AND HIGH-K GATES
    30.
    发明申请
    METHOD OF MAKING A FINFET DEVICE STRUCTURE HAVING DUAL METAL AND HIGH-K GATES 失效

    公开(公告)号：US20090148986A1

    公开(公告)日：2009-06-11

    申请号：US11951552

    申请日：2007-12-06

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L21/04

    CPC分类号： H01L29/785 ,  H01L27/1211 ,  H01L29/517 ,  H01L29/66795

    摘要： A method of making a FinFET device structure, includes: providing a semiconductor-on-insulator (SOI) substrate having a semiconductor layer on an insulating layer on a base (e.g., semiconductor) layer; forming a cap layer (e.g., silicon nitride) on the SOI substrate; forming, on the insulating layer, first and second semiconductor fins with a first cap layer on the first fin and a second cap layer on the second fin; providing a first high-k dielectric layer across the first and the second cap layers and the first and second fins; providing a first metal layer onto the first high-k dielectric layer; providing a first semiconductor layer onto the first metal layer; removing the first semiconductor layer, the first metal layer, and the first high-k dielectric layer from the second cap layer, the second fin and from regions adjacent to the second fin; providing a second high-k dielectric layer onto the second cap layer, the second fin and a portion of the first metal layer; providing a second metal layer onto the second high-k dielectric layer, the second metal layer having a composition different than the first metal layer; providing a second semiconductor layer onto the second metal layer in a region above the second cap layer and into the regions adjacent to the second fin; removing the second semiconductor layer from the second metal layer in the region above the second cap layer, from adjoining regions and from the regions adjacent to the second fin; removing the second metal layer and the second high-k dielectric layer from a region above the first cap layer and from adjoining regions above the first semiconductor layer; removing the first metal layer, the first high-k dielectric layer, the first semiconductor layer, the second metal layer, the second high-k dielectric layer and the second semiconductor layer from regions above a plane containing top surfaces of the first and the second cap layers; forming first and second gates; forming respective source and drain regions within portions of the first and the second fins adjacent to the first and second gates, and then removing portions of the first and the second semiconductor layers, the first and the second high-k dielectric layers and the first and the second metal layers from a medial region between the first and the second fins.