公开(公告)号：US20110147828A1

公开(公告)日：2011-06-23

申请号：US12643912

申请日：2009-12-21

申请人： Anand S. Murthy ,  Daniel Bourne Aubertine ,  Tahir Ghani ,  Abhijit Javant Pethe

发明人： Anand S. Murthy ,  Daniel Bourne Aubertine ,  Tahir Ghani ,  Abhijit Javant Pethe

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28079 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

摘要： Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

摘要翻译： 本发明的实施例描述了半导体器件上的外延区域。 在一个实施例中，通过循环沉积蚀刻工艺将外延区域沉积到衬底上。 在循环沉积 - 蚀刻工艺期间在间隔物下方产生的腔被外延盖层回填。 外延区和外延盖层改善沟道区的电子迁移率，减少短沟道效应并降低寄生电阻。

公开(公告)号：US20110147816A1

公开(公告)日：2011-06-23

申请号：US12642342

申请日：2009-12-18

申请人： Dmitri E. Nikonov ,  George I. Bourianoff ,  Tahir Ghani

发明人： Dmitri E. Nikonov ,  George I. Bourianoff ,  Tahir Ghani

IPC分类号： H01L29/82 ,  H01L21/28

CPC分类号： H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/093 ,  G01R33/1284 ,  G11C11/161 ,  H01F10/133 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/307 ,  H01L27/22 ,  H01L27/228 ,  H01L43/12

摘要： Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer.

摘要翻译： 描述了自旋扭矩磁集成电路及其装置。 自旋扭矩磁集成电路包括设置在基板上方的第一自由铁磁层。 非磁性层设置在第一自由铁磁层的上方。 包括多个写柱和多个读柱，每个柱设置在非磁性层之上并且包括固定的铁磁层。

公开(公告)号：US07226824B2

公开(公告)日：2007-06-05

申请号：US10918818

申请日：2004-08-13

申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

IPC分类号： H01L21/338

CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

公开(公告)号：US20060151832A1

公开(公告)日：2006-07-13

申请号：US11233854

申请日：2005-09-09

申请人： Anand Murthy ,  Robert Chau ,  Tahir Ghani

发明人： Anand Murthy ,  Robert Chau ,  Tahir Ghani

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US20050184311A1

公开(公告)日：2005-08-25

申请号：US11107141

申请日：2005-04-14

申请人： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

发明人： Anand Murthy ,  Robert Chau ,  Tahir Ghani ,  Kaizad Mistry

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IATAT和/或DLIN 。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US06777760B1

公开(公告)日：2004-08-17

申请号：US09477870

申请日：2000-01-05

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J Keating ,  Alan Myers

IPC分类号： H01L2994

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06506652B2

公开(公告)日：2003-01-14

申请号：US09458357

申请日：1999-12-09

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06188117B1

公开(公告)日：2001-02-13

申请号：US09276477

申请日：1999-03-25

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L3300

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved polycide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下多晶硅栅极中提高多晶硅栅极电阻的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US5798552A

公开(公告)日：1998-08-25

申请号：US889718

申请日：1997-07-08

申请人： Mohsen Alavi ,  Tahir Ghani

发明人： Mohsen Alavi ,  Tahir Ghani

IPC分类号： H01L29/10 ,  H03K17/10 ,  H01L29/76 ,  H01L29/94

CPC分类号： H03K17/102 ,  H01L29/1079

摘要： A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized. Furthermore, with the transistor layout described herein having at least a portion of the first diffusion region disposed within the well, adequate device isolation is also realized.

公开(公告)号：US20190259699A1

公开(公告)日：2019-08-22

申请号：US16348116

申请日：2016-12-23

申请人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC分类号： H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/306 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234

摘要： Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.