公开(公告)号：US20070001264A1

公开(公告)日：2007-01-04

申请号：US11516007

申请日：2006-09-06

申请人： David Sheridan ,  Peter Gray ,  Jeffrey Johnson ,  Qizhi Liu

发明人： David Sheridan ,  Peter Gray ,  Jeffrey Johnson ,  Qizhi Liu

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/0821 ,  H01L29/7378

摘要： A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

摘要翻译： 使用可用的硅锗（SiGe）低温外延层的一部分作为垂直NPN晶体管的升高的基极区域和与垂直PNP集电极层相同的SiGe LTE层的另一部分来制造互补双极晶体管。 互补的晶体管对垂直对齐并在单个方向上工作。

公开(公告)号：US20060124964A1

公开(公告)日：2006-06-15

申请号：US11288843

申请日：2005-11-29

申请人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

发明人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L31/109

CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

公开(公告)号：US07002221B2

公开(公告)日：2006-02-21

申请号：US10604988

申请日：2003-08-29

申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

IPC分类号： H01L23/62

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

公开(公告)号：US20050199908A1

公开(公告)日：2005-09-15

申请号：US10708598

申请日：2004-03-13

申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US06271127B1

公开(公告)日：2001-08-07

申请号：US09329569

申请日：1999-06-10

申请人： Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

发明人： Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76825 ,  Y10S438/949

摘要： Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.

摘要翻译： 用于半导体工件的双镶嵌金属化的方法，其使用在绝缘体中产生蚀刻停止的工艺，从而消除了沉积蚀刻停止层的需要。 使用电子束曝光来固化绝缘体或具有低介电常数的材料。 将电子束应用于低介电常数材料将低介电常数材料的最上层转化为蚀刻停止层，同时快速热加热固化低介电常数材料的其余部分。 在低介电常数材料中形成蚀刻停止层也可以通过使用离子注入固化低介电常数材料来实现。

公开(公告)号：US08932931B2

公开(公告)日：2015-01-13

申请号：US13371605

申请日：2012-02-13

申请人： Margaret A. Faucher ,  Paula M. Fisher ,  Thomas H. Gabert ,  Joseph P. Hasselbach ,  Qizhi Liu ,  Glenn C. MacDougall

发明人： Margaret A. Faucher ,  Paula M. Fisher ,  Thomas H. Gabert ,  Joseph P. Hasselbach ,  Qizhi Liu ,  Glenn C. MacDougall

IPC分类号： H01L21/331 ,  H01L29/66

CPC分类号： H01L29/732 ,  H01L21/76221 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/737 ,  H01L29/7371

摘要： Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

摘要翻译： 本发明的方面提供了形成双极结型晶体管的方法。 该方法包括：在发射台上设置包括均匀的氮化硅层的半导体衬底，以及在发射极底座下面的基底层; 在基区的第一端和第二端应用光掩模; 以及用所述光掩模进行氮化硅蚀刻以同时形成与所述发射极基座相邻的氮化硅间隔体，并暴露所述双极结型晶体管的基极区域。 氮化硅蚀刻可以是端点蚀刻。

公开(公告)号：US08853043B2

公开(公告)日：2014-10-07

申请号：US13610641

申请日：2012-09-11

申请人： Wade J. Hodge ,  Alvin J. Joseph ,  Rajendran Krishnasamy ,  Qizhi Liu ,  Bradley A. Orner

发明人： Wade J. Hodge ,  Alvin J. Joseph ,  Rajendran Krishnasamy ,  Qizhi Liu ,  Bradley A. Orner

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L29/737 ,  H01L29/10 ,  H01L21/8249

CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L29/1004

摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。

公开(公告)号：US08786051B2

公开(公告)日：2014-07-22

申请号：US13401064

申请日：2012-02-21

申请人： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

发明人： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

IPC分类号： H01L21/02

CPC分类号： H01L29/732 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

摘要： Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.

摘要翻译： 公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。 晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。 相对薄的种子层覆盖沟槽隔离区域和收集器区域。 该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。 本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。 非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。

公开(公告)号：US08728897B2

公开(公告)日：2014-05-20

申请号：US13342797

申请日：2012-01-03

申请人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

发明人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC分类号： H01L21/336

CPC分类号： H01L29/66242 ,  H01L21/76232 ,  H01L22/20 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7371

摘要： A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer.

摘要翻译： 提供了通过应变补偿和制造方法提高驱动电流的功率SiGe异质结双色晶体管（HBT）。 一种方法包括在包括子集电极层，集电极层，基极缓冲层，基极层和发射极缓冲层的器件的层中以连续稳定的浓度添加碳。

公开(公告)号：US20140021547A1

公开(公告)日：2014-01-23

申请号：US13553947

申请日：2012-07-20

申请人： William F. Clark, JR. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

发明人： William F. Clark, JR. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L27/088 ,  H01L21/265

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。