公开(公告)号：US6153896A

公开(公告)日：2000-11-28

申请号：US41792

申请日：1998-03-13

申请人： Ichiro Omura ,  Wolfgang Fichtner ,  Hiromichi Ohashi ,  Tsuneo Ogura ,  Hideaki Ninomiya

发明人： Ichiro Omura ,  Wolfgang Fichtner ,  Hiromichi Ohashi ,  Tsuneo Ogura ,  Hideaki Ninomiya

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/739 ,  H01L29/78 ,  H03K17/0812

CPC分类号： H01L29/7395 ,  H03K17/08128

摘要： Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations and the like, thereby improving reliability, and a method for controlling the semiconductor device. The semiconductor device comprises an n-type base layer, a p-type emitter layer, which is formed on a surface of the n-type base layer, a collector electrode, formed on a surface of the p-type emitter layer, a p-type base layer, formed on a surface on the n-type base layer which is opposite to the p-type emitter layer, an n-type source layer, formed in a surface of the p-type base layer, an emitter electrode, formed on the n-type source layer and the p-type base layer, and a gate electrode, contacting the n-type source layer, the p-type base layer and the n-type base layer, with a gate insulating film interposed therebetween, wherein when a voltage is applied between the collector electrode and the emitter electrode, the capacitance of the gate electrode is always a positive value or zero.

公开(公告)号：US5340806A

公开(公告)日：1994-08-23

申请号：US850720

申请日：1993-01-07

申请人： Kiichi Sawai ,  Masayasu Kurono ,  Juichi Awaya ,  Akio Kojima ,  Hideaki Ninomiya ,  Yoshiro Ishiwata ,  Masahiro Nakajima

发明人： Kiichi Sawai ,  Masayasu Kurono ,  Juichi Awaya ,  Akio Kojima ,  Hideaki Ninomiya ,  Yoshiro Ishiwata ,  Masahiro Nakajima

IPC分类号： A61K31/28 ,  A61K31/79 ,  A61K31/555

CPC分类号： A61K31/28

摘要： A composition comprising an organogermanium compound represented by the formula ##STR1## wherein n is an integer of 1 or more, R is hydrogen, alkyl, --COOH, --COOR', phenyl, ##STR2## and R' is a lower alkyl and a high molecular carrier, as well as an immunity adjusting agent comprising the composition. The treatment of hepatitis with compositions containing this germanium derivative.

摘要翻译： 一种组合物，其包含由式（I）表示的有机锗化合物，其中n为1以上的整数，R为氢，烷基，-COOH，-COOR'，苯基，或者图像 >和R'是低级烷基和高分子载体，以及包含该组合物的免疫调节剂。 用含锗衍生物的组合物治疗肝炎。

公开(公告)号：US4111578A

公开(公告)日：1978-09-05

申请号：US547775

申请日：1975-02-07

申请人： Kuniaki Sato ,  Yoshihiro Nakamura ,  Hideaki Ninomiya

发明人： Kuniaki Sato ,  Yoshihiro Nakamura ,  Hideaki Ninomiya

IPC分类号： E04B1/24 ,  F16B7/00

CPC分类号： E04B1/2403 ,  E04B2001/2415 ,  E04B2001/2448 ,  Y10T403/3913 ,  Y10T403/4691

摘要： Fittings for connecting columns and beams of a steel frame construction, each comprising a substantially rectangular base plate to be connected to the column by means of high strength bolts and having centrally a horizontally continuous thicker portion from which the base plate is tapered toward upper and lower edges, a horizontal protrusion projecting from the thicker portion in opposition to a flange of the beam and vertical protrusion in opposition to a web of the beam and projecting from the base plate to form with the horizontal protrusion a T-shaped protrusion.

公开(公告)号：US4110260A

公开(公告)日：1978-08-29

申请号：US725457

申请日：1976-09-22

申请人： Hirotaka Yamamoto ,  Satoshi Sendai ,  Hideaki Ninomiya

发明人： Hirotaka Yamamoto ,  Satoshi Sendai ,  Hideaki Ninomiya

IPC分类号： C04B35/01 ,  C04B35/71 ,  H01B1/00 ,  H01B1/08

CPC分类号： C04B35/71 ,  C04B35/01 ,  H01B1/00

摘要： The electroconductive composite ceramics composed of an independent phase conglomerates having a particle diameter of at least 20.mu. and a continuous phase connecting mutually the independent phase of conglomerates. Particularly, electroconductive composite ceramics composed of (A) 50-98% by weight of an independent phase of conglomerates having a particle diameter of at least 20 which consists essentially of a phase of insulating or semiconductive ceramics having a high melting point or a mixture thereof and (B) 50-2% by weight of a continuous phase of an electroconductive substance connecting mutually the independent phase of conglomerates. The electroconductive composite ceramics exhibit stable electroconductivity-temperature characteristics at a temperature of 1000.degree. C. or higher and have excellent thermal shock resistance, mechanical strength and chemical resistance.

摘要翻译： 导电复合陶瓷由具有至少20微米的粒径的砾石的独立相组成，连续相连接相互独立的砾岩相。 特别地，导电复合陶瓷由（A）50-98重量％的粒径为至少为20的砾石的独立相组成，其主要由具有高熔点的绝缘或半导体陶瓷相或其混合物组成 和（B）50-2重量％的连续相的连续相连接相互独立相的砾岩。 导电性复合陶瓷在1000℃以上的温度下表现出稳定的导电性特性，具有优异的耐热冲击性，机械强度和耐化学性。

公开(公告)号：US08319314B2

公开(公告)日：2012-11-27

申请号：US13005589

申请日：2011-01-13

申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/739 ,  H01L27/082 ,  H01L29/00 ,  H01L21/02

CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。

公开(公告)号：US07456487B2

公开(公告)日：2008-11-25

申请号：US10974810

申请日：2004-10-28

申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

摘要： This disclosure concerns a semiconductor device that includes a first base layer; second base layers provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers; an emitter layer formed on a surface of the second base layers; a collector layer provided below a second surface of the first base layer, an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being electrically isolated from the emitter layer and the second base layers, wherein the space section includes a semiconductor layer being deeper than the second base layers.

摘要翻译： 本公开涉及包括第一基底层的半导体器件; 设置在所述第一基底层的第一表面的一部分上的第二基底层; 形成在第二基层的每侧的沟槽; 形成在所述第二基底层的表面上的发射极层; 设置在所述第一基底层的第二表面下方的集电极层，形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在沟槽内并由绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，所述空间部分与发射极层和第二基底层电隔离，其中所述空间部分包括比所述第二基底层更深的半导体层。

公开(公告)号：US20070278566A1

公开(公告)日：2007-12-06

申请号：US11833401

申请日：2007-08-03

申请人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/78

CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7397

摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。

公开(公告)号：US20060237786A1

公开(公告)日：2006-10-26

申请号：US11384260

申请日：2006-03-21

申请人： Hideaki Ninomiya ,  Masanobu Tsuchitani ,  Satoshi Teramae ,  Masakazu Yamaguchi ,  Koichi Sugiyama ,  Satoshi Urano ,  Keiko Kawamura

发明人： Hideaki Ninomiya ,  Masanobu Tsuchitani ,  Satoshi Teramae ,  Masakazu Yamaguchi ,  Koichi Sugiyama ,  Satoshi Urano ,  Keiko Kawamura

IPC分类号： H01L29/76

CPC分类号： H01L29/7397 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7393

摘要： A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electrically connected to the first conductive type base layer and the second conductive type base layer; and a first conductive type or second conductive type floating layer formed on the bottom of the insulation layer.

摘要翻译： 根据本发明的功率半导体器件包括：第一导电型基极层; 选择性地形成在所述第一导电型基底层上的第二导电型基底层; 形成在不形成第二导电型基底层的第一导电型基底层上的区域中的绝缘层; 形成在形成在第二导电型基极层和绝缘层之间的沟槽的内表面上以便将它们彼此分离并从第二导电类型基底的表面到达第一导电型基极的栅极绝缘膜 层; 选择性地形成在与所述栅极绝缘膜接触的所述第二导电型基底层的表面上的第一导电型源极层; 形成在所述沟槽中的栅电极，通过所述栅极绝缘膜与所述第一导电型基极层，所述第二导电型基极层和所述第一导电型源极绝缘; 电连接到第一导电型基极层和第二导电型基极层的主电极; 以及形成在绝缘层的底部上的第一导电型或第二导电型浮动层。

公开(公告)号：US07078740B2

公开(公告)日：2006-07-18

申请号：US10843571

申请日：2004-05-12

申请人： Masakazu Yamaguchi ,  Hideaki Ninomiya ,  Ichiro Omura ,  Tomoki Inoue

发明人： Masakazu Yamaguchi ,  Hideaki Ninomiya ,  Ichiro Omura ,  Tomoki Inoue

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L29/0696 ,  H01L29/0619 ,  H01L29/0839 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397

摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

公开(公告)号：US06980066B2

公开(公告)日：2005-12-27

申请号：US10473019

申请日：2002-03-27

申请人： Shinya Nakai ,  Yoshinari Yamashita ,  Hideaki Ninomiya

发明人： Shinya Nakai ,  Yoshinari Yamashita ,  Hideaki Ninomiya

IPC分类号： H05K1/14 ,  H01L23/13 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H03B5/18 ,  H03H9/72 ,  H04B1/40 ,  H04B1/48 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/46 ,  H03H7/38 ,  H01P3/08 ,  H03H7/46

CPC分类号： H05K1/142 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15313 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03H9/0542 ,  H03H9/0557 ,  H04B1/406 ,  H04B1/48 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/183 ,  H05K3/4614 ,  H05K3/4697 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： It is an object of the present invention to provide a high-frequency module whose production yield as a complete module can be prevented from being lowered. The high-frequency module according to the present invention includes a main module including a first high-frequency circuit at least a part of which is constituted by a conductive pattern built in a multi-layered substrate and a sub-module including a second high-frequency circuit, and the sub-module is inserted into a cavity formed in the main module. According to the present invention, the main module including the first high-frequency circuit and the sub-module including the second high-frequency circuit are constituted as separate components and the main module and the sub-module are integrated by inserting the sub-module into the cavity formed in the main module. Therefore, it is possible to use only a main module and sub-module that have been inspected after manufacture and found to be non-defective. Accordingly, it is possible to markedly increase the yield of the high-frequency module as a whole.

摘要翻译： 本发明的目的是提供一种高频模块，其可以防止作为完整模块的生产率降低。 根据本发明的高频模块包括：主模块，其包括第一高频电路，其至少一部分由内置在多层基板中的导电图案和包括第二高频电路的子模块构成; 频率电路，并且子模块插入形成在主模块中的空腔中。 根据本发明，包括第一高频电路和包括第二高频电路的子模块的主模块被构成为单独的组件，并且主模块和子模块通过插入子模块 进入主模块中形成的空腔。 因此，可以仅使用在制造后被检查的主模块和子模块，并且发现是无缺陷的。 因此，可以显着地提高高频模块的整体产量。