公开(公告)号：US5122600A

公开(公告)日：1992-06-16

申请号：US411127

申请日：1989-09-22

申请人： Haruma Kawaguchi ,  Akira Asai ,  Yasuji Ohtsuka ,  Hiroshi Handa

发明人： Haruma Kawaguchi ,  Akira Asai ,  Yasuji Ohtsuka ,  Hiroshi Handa

IPC分类号： C12N15/09 ,  C07K1/14 ,  C07K1/16 ,  C07K1/22 ,  C07K14/47 ,  C12N15/00 ,  C12P21/00

CPC分类号： C07K14/47

摘要： There are disclosed a DNA-immobilized microsphere comprising DNA chains having base sequences which bind a specific protein specifically, and a carrier having a particle size of not more than 50 .mu.m and not less than 0.01 .mu.m which does not adsorb any protein, said carrier and said DNA chains being bound to each other by a chemical bond, and a process for purifying a protein using said microsphere.

摘要翻译： 公开了包含具有特异性结合特定蛋白质的碱基序列的DNA链的DNA固定化微球和不吸附任何蛋白质的粒径不大于50μm且不小于0.01μm的载体，所述 载体和所述DNA链通过化学键彼此结合，以及使用所述微球纯化蛋白质的方法。

公开(公告)号：US07564073B2

公开(公告)日：2009-07-21

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L27/04

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US07319943B2

公开(公告)日：2008-01-15

申请号：US10735143

申请日：2003-12-11

申请人： Teruyoshi Washizawa ,  Akira Asai ,  Masayoshi Tachihara ,  Katsuhiko Sinjo ,  Nobuhiro Yoshikawa

发明人： Teruyoshi Washizawa ,  Akira Asai ,  Masayoshi Tachihara ,  Katsuhiko Sinjo ,  Nobuhiro Yoshikawa

IPC分类号： G06F17/50 ,  G06F9/00

CPC分类号： G06F17/11

摘要： In an optimum design method comprising a first solution determining step of solving an optimization problem of a first evaluation function for a state variable vector with a design variable vector being as a parameter, and a second solution determining step of solving an optimization problem of a second evaluation function for the design variable vector and the state variable vector thus obtained, the second solution determining step includes the steps of computing a gradient vector of the second evaluation function for the design variable vector, computing a first coefficient based on a value of a norm of the gradient vector, computing a search vector based on the first coefficient, computing a second coefficient, and updating the design variable vector based on the second coefficient. The second coefficient computing step includes the first solution determining step, the first solution determining step is executed as an iterative method based on the gradient vector, and the state variable vector is not initialized during iteration. The optimum design method is precisely adaptable for structural changes.

摘要翻译： 一种最优设计方法，包括：第一解决方案确定步骤，用于以设计变量向量作为参数来求解用于状态变量向量的第一评估函数的优化问题;以及第二解决方案确定步骤，用于求解第二 第二解决方案确定步骤包括以下步骤：计算用于设计变量向量的第二评估函数的梯度向量，基于规范的值计算第一系数;对于设计变量向量和状态变量向量的评估函数， 的梯度向量，基于第一系数计算搜索向量，计算第二系数，并且基于第二系数更新设计变量向量。 第二系数计算步骤包括第一解决方案确定步骤，基于梯度向量作为迭代方法执行第一解决方案确定步骤，并且在迭代期间不初始化状态变量向量。 最佳设计方法适用于结构变化。

公开(公告)号：US20070052041A1

公开(公告)日：2007-03-08

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由所述连接部的至少一部分在所述连接部的长度方向上形成的通路区域（15a） 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US20060054944A1

公开(公告)日：2006-03-16

申请号：US11260197

申请日：2005-10-28

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

摘要翻译： 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US06893934B2

公开(公告)日：2005-05-17

申请号：US10603737

申请日：2003-06-26

申请人： Teruhit Ohnishi ,  Akira Asai

发明人： Teruhit Ohnishi ,  Akira Asai

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

摘要翻译： 作为由i-Si 1-x Ge x x构成的基底的Si 1-x Ge 2 x层111b， / SUB层，并且在集电极层102上形成有Si + 1-xSi Ge层，并且Si覆盖层111a 因为发射极形成在p + 1 Si 1-x Ge层上。 发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的N +和/或多个多晶硅层129b组成， 在基底开口118中的Si覆盖层111a上形成含有高浓度磷的多晶硅层129a。 通过抑制Si覆盖层111a以过高的浓度掺杂磷（P）来适当地维持基层中的杂质浓度分布。 Si覆盖层111a的上部可以含有p型杂质。 因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

公开(公告)号：US20050092230A1

公开(公告)日：2005-05-05

申请号：US11009020

申请日：2004-12-13

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： C30B1/00 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/322 ,  H01L21/324

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06869971B1

公开(公告)日：2005-03-22

申请号：US10110964

申请日：2000-10-19

申请人： Tsutomu Akama ,  Akira Asai ,  Tsutomu Agatsuma ,  Shinji Nara ,  Yoshinori Yamashita ,  Tamio Mizukami ,  Shun-ichi Ikeda ,  Yutaka Saitoh ,  Yutaka Kanda

发明人： Tsutomu Akama ,  Akira Asai ,  Tsutomu Agatsuma ,  Shinji Nara ,  Yoshinori Yamashita ,  Tamio Mizukami ,  Shun-ichi Ikeda ,  Yutaka Saitoh ,  Yutaka Kanda

IPC分类号： A61P31/04 ,  A61P35/00 ,  C07D487/04 ,  C07D487/14 ,  C07D487/16 ,  C07D491/14 ,  C07D491/147 ,  C07D491/16 ,  C07D498/08 ,  A61K31/403 ,  A61K31/4453 ,  C07D209/52 ,  C07D401/06

CPC分类号： C07D487/04 ,  C07D487/14 ,  C07D491/14

摘要： UCS 1025 derivatives having antitumor activity or antibacterial activity which are represented by formula (I): wherein R1 represents hydrogen, lower alkyl, etc.; R2 represents hydrogen, or is combined with R3 to represent a bond, etc., or is combined with R4 to represent —O(C═O)—, etc.; R3 represents hydrogen, etc., or is combined with R2 to represent a bond, etc.; R4 represents hydrogen, etc., or is combined with R2 to represent —(C═O)O—, etc.; R5 represents hydrogen or is combined with R6 to represent a bond; R6 represents hydrogen, etc., or is combined with R5 to represent a bond; R7 represents hydrogen or is combined with R8 to represent ═O; R8 represents hydroxy or is combined with R7 to represent ═O; ---- represents a single bond or a double bond, and a represents a single bond (two carbon atoms to which a is bound are combined to form a single bond) or an oxygen atom, or pharmaceutically acceptable salts thereof.

摘要翻译： 由式（I）表示的具有抗肿瘤活性或抗菌活性的UCS 1025衍生物：其中R 1表示氢，低级烷基等; R 2表示氢，或与R 3结合以表示键等，或与R 4结合以表示-O（C = O） - 等; R 3表示氢等，或与R 2结合以表示键等; R 4表示氢等，或与R 2结合代表 - （C = O）O-等; R 5表示氢或与R 6结合以表示键; R 6表示氢等，或与R 5结合以表示键; R 7表示氢或与R 8结合以代表= O; R 8表示羟基或与R 7结合代表= O; ----表示单键或双键，a表示单键（被结合形成单键的两个碳原子）或氧原子，或其药学上可接受的盐。

公开(公告)号：US06674149B2

公开(公告)日：2004-01-06

申请号：US10009201

申请日：2001-12-10

申请人： Teruhito Ohnishi ,  Akira Asai

发明人： Teruhito Ohnishi ,  Akira Asai

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

摘要翻译： 在集电极层102上形成用作由i-Si1-xGex层和ap + Si1-xGex层构成的基底的Si1-xGex层111b，在p上形成作为发射极的Si覆盖层111a Si1-xGex层。 发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的n +多晶硅层129b和含有磷的多晶硅层129a组成 在基底开口118中的Si覆盖层111a上形成高浓度。通过抑制Si覆盖层111a以过高的浓度掺杂磷（P）来适当地保持基底层中的杂质浓度分布。 Si覆盖层111a的上部可以含有p型杂质。 因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

公开(公告)号：US06642607B2

公开(公告)日：2003-11-04

申请号：US10061365

申请日：2002-02-04

申请人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

发明人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC分类号： H01L2993

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

摘要翻译： 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。