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公开(公告)号：US10892010B2
公开(公告)日：2021-01-12
申请号：US16274301
申请日：2019-02-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuang-Hao Chiang , Yu-Hsuan Lin
Abstract: A method for controlling accumulated resistance property of a ReRAM device, wherein the method includes steps as follows: A first programing pulse set is firstly applied to a ReRAM device for acquiring a reference accumulated resistance distribution. A second programing pulse set is then provided according to the reference accumulated resistance distribution, and the second programing pulse set is applied to the ReRAM device, to make the ReRAM device having a predetermined accumulated resistance distribution.
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公开(公告)号：US09747980B2
公开(公告)日：2017-08-29
申请号：US15139367
申请日：2016-04-27
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ming-Hsiu Lee , Yu-Hsuan Lin
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/04 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0038 , G11C2013/0045 , G11C2013/005 , G11C2213/79 , H01R13/405 , H01R13/502
Abstract: A semiconductor device includes: a physical parameter sensing circuit configured to sense a variation of a physical parameter; an applying parameter generating circuit coupled to the physical parameter sensing circuit, configured to adjust an applying parameter from the variation of the physical parameter based on a transfer function which defines relationship between the physical parameter and the applying parameter; and a main circuit, coupled to the physical parameter sensing circuit and the applying parameter generating circuit, wherein the applying parameter generated by the applying parameter generating circuit is used to compensate effect on operations of the main circuit caused by the variation of the physical parameter.
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公开(公告)号：US12260917B2
公开(公告)日：2025-03-25
申请号：US18623116
申请日：2024-04-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Dai-Ying Lee , Ming-Hsiu Lee
Abstract: A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.
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公开(公告)号：US12159672B2
公开(公告)日：2024-12-03
申请号：US18162728
申请日：2023-02-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Yu-Hsuan Lin , Tian-Cih Bo , Feng-Min Lee , Yu-Yu Lin
Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.
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公开(公告)号：US12094534B2
公开(公告)日：2024-09-17
申请号：US18459461
申请日：2023-09-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Po-Hao Tseng
CPC classification number: G11C15/046 , G11C7/14
Abstract: The application provides a content addressable memory (CAM) memory device, a CAM cell and a method for searching and comparing data thereof. The CAM device includes: a plurality of CAM cells; and an electrical characteristic detection circuit coupled to the CAM cells; wherein in data searching, a search data is compared with a storage data stored in the CAM cells, the CAM cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.
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Patent Agency Ranking
26.发明授权公开(公告)号：US12069857B2
公开(公告)日：2024-08-20
申请号：US17408535
申请日：2021-08-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Feng-Min Lee , Po-Hao Tseng
CPC classification number: H10B41/35 , H01L29/40114 , H01L29/66825
Abstract: The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.
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公开(公告)号：US11984166B2
公开(公告)日：2024-05-14
申请号：US17388079
申请日：2021-07-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Dai-Ying Lee , Ming-Hsiu Lee
CPC classification number: G11C16/102 , G11C16/26 , G11C16/3459 , G11C29/40 , G11C2029/4002
Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.
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公开(公告)号：US11790990B2
公开(公告)日：2023-10-17
申请号：US17717192
申请日：2022-04-11
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Po-Hao Tseng
CPC classification number: G11C15/046 , G11C7/14
Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.
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公开(公告)号：US20230253032A1
公开(公告)日：2023-08-10
申请号：US18303194
申请日：2023-04-19
Applicant: MACRONIX International Co., Ltd.
Inventor： Yu-Hsuan Lin , Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
IPC: G11C11/4093 , G11C11/4091 , G06F7/523 , G11C11/408 , G06F7/501 , G11C11/4094
CPC classification number: G11C11/4093 , G11C11/4091 , G06F7/523 , G11C11/4085 , G06F7/501 , G11C11/4094
Abstract: An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.
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公开(公告)号：US11664070B2
公开(公告)日：2023-05-30
申请号：US17344555
申请日：2021-06-10
Applicant: MACRONIX International Co., Ltd.
Inventor： Yu-Hsuan Lin , Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
IPC: G11C11/4093 , G11C11/4091 , G11C11/408 , G11C11/4094 , G06F7/523 , G06F7/501
CPC classification number: G11C11/4093 , G06F7/501 , G06F7/523 , G11C11/4085 , G11C11/4091 , G11C11/4094
Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.
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