中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.046 seconds)

    SEMICONDUCTOR PACKAGE ASSEMBLY
    23.
    发明申请
    SEMICONDUCTOR PACKAGE ASSEMBLY 审中-公开

    公开(公告)号：US20160079205A1

    公开(公告)日：2016-03-17

    申请号：US14932147

    申请日：2015-11-04

    Applicant: MediaTek Inc.

    Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

    IPC: H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/12

    Abstract: The invention provides a semiconductor package, a semiconductor package assembly and a method for fabricating a semiconductor package. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. Conductive pillar structures are disposed on a surface of the first RDL structure away from the first semiconductor die, wherein the conductive pillar structures are coupled to the first RDL structure.

    Abstract translation: 本发明提供半导体封装，半导体封装组件和用于制造半导体封装的方法。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一再分配层（RDL）结构耦合到第一半导体管芯。 导电柱结构设置在远离第一半导体管芯的第一RDL结构的表面上，其中导电柱结构耦合到第一RDL结构。

    SEMICONDUCTOR PACKAGE STRUCTURE
    24.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权

    公开(公告)号：US20220336374A1

    公开(公告)日：2022-10-20

    申请号：US17810625

    申请日：2022-07-04

    Applicant: MEDIATEK INC.

    Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG ,  Nai-Wei LIU

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/043 ,  H01L23/13 ,  H01L23/538

    Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. A hole is formed on a surface of the substrate, wherein the hole is located within projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material, surrounding the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate, are exposed by the molding material.

    SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERS
    25.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERS 有权

    公开(公告)号：US20220020726A1

    公开(公告)日：2022-01-20

    申请号：US17488921

    申请日：2021-09-29

    Applicant: MEDIATEK INC.

    Inventor： Chia-Cheng CHANG ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Yi-Jou LIN

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

    Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.

    SEMICONDUCTOR PACKAGE STRUCTURE
    26.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权

    公开(公告)号：US20210159177A1

    公开(公告)日：2021-05-27

    申请号：US17098659

    申请日：2020-11-16

    Applicant: MEDIATEK INC.

    Inventor： Yi-Lin TSAI ,  Yi-Jou LIN ,  I-Hsuan PENG ,  Wen-Sung HSU

    IPC: H01L23/538 ,  H01L23/00

    Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.

    SEMICONDUCTOR PACKAGE ASSEMBLY
    27.
    发明申请
    SEMICONDUCTOR PACKAGE ASSEMBLY 审中-公开

    公开(公告)号：US20190131233A1

    公开(公告)日：2019-05-02

    申请号：US16232129

    申请日：2018-12-26

    Applicant: MEDIATEK INC.

    Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

    IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

    SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME
    28.
    发明申请
    SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20190043848A1

    公开(公告)日：2019-02-07

    申请号：US16043326

    申请日：2018-07-24

    Applicant: MEDIATEK INC.

    Inventor： Chia-Cheng CHANG ,  I-Hsuan PENG ,  Tzu-Hung LIN

    IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

    SEMICONDUCTOR PACKAGE STRUCTURE
    29.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20180269164A1

    公开(公告)日：2018-09-20

    申请号：US15906098

    申请日：2018-02-27

    Applicant: MEDIATEK INC.

    Inventor： Tzu-Hung LIN ,  Chia-Cheng CHANG ,  I-Hsuan PENG ,  Nai-Wei LIU

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/043 ,  H01L23/31 ,  H01L25/065

    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.

Patent Agency Ranking