公开(公告)号：US20200051615A1

公开(公告)日：2020-02-13

申请号：US16658147

申请日：2019-10-20

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu ,  Shang-Pin Chen

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  G06F13/40 ,  G11C5/04

Abstract: The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.

公开(公告)号：US10141044B2

公开(公告)日：2018-11-27

申请号：US15247870

申请日：2016-08-25

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Chia-Yu Chan ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22

Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.

公开(公告)号：US10083728B2

公开(公告)日：2018-09-25

申请号：US14324228

申请日：2014-07-06

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

IPC: G06F12/00 ,  G11C8/12 ,  G06F13/16

CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

公开(公告)号：US20170243629A1

公开(公告)日：2017-08-24

申请号：US15424882

申请日：2017-02-05

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4093 ,  G11C2207/105 ,  H03K19/0005 ,  H04L25/0298

Abstract: A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.

公开(公告)号：US20170243628A1

公开(公告)日：2017-08-24

申请号：US15390692

申请日：2016-12-26

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4093 ,  G11C2207/105 ,  H03K19/0005 ,  H04L25/0298

Abstract: A memory system includes a memory controller and a memory module, where the memory controller is arranged for generating at least a first clock signal and an inverted first clock signal, and the memory module is arranged to receive at least the first clock signal and the inverted first clock signal from the memory controller. In addition, the memory module includes a termination module, and the first clock signal is coupled to the inverted first clock signal through the termination module.

公开(公告)号：US20170147030A1

公开(公告)日：2017-05-25

申请号：US15424891

申请日：2017-02-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0994 ,  H03L2207/50

Abstract: A method for performing signal control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of the electronic device (e.g. signals of a memory interface circuit of the electronic device); applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the data signal is calibrated with respect to the clock signal with aid of the at least one phase shift.

公开(公告)号：US20160173093A1

公开(公告)日：2016-06-16

申请号：US14830755

申请日：2015-08-20

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  An-Siou Li

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018507

Abstract: A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving control signal and a second driving control signal according to a data signal, wherein the second driving control signal transits in response to a transition of the data signal, and the first driving control signal includes a pulse corresponding to the transition of the data signal; and utilizing a first switching unit to control a first signal path between a first voltage level and an output terminal of an output stage according to the first driving control signal, and utilizing a second switching unit to control a second signal path between the first voltage level and the output terminal according to the second driving control signal, wherein a first impedance of the first signal path is less than a second impedance of the second signal path.

Abstract translation: 提供了一种在电子设备和相关设备中执行信号驱动控制的方法。 该方法包括：根据数据信号产生第一驱动控制信号和第二驱动控制信号，其中第二驱动控制信号响应于数据信号的转变而转换，并且第一驱动控制信号包括对应于 数据信号的转换; 以及利用第一开关单元根据第一驱动控制信号来控制输出级的第一电压电平和输出端之间的第一信号路径，并且利用第二开关单元来控制第一电压电平 以及根据第二驱动控制信号的输出端子，其中第一信号路径的第一阻抗小于第二信号路径的第二阻抗。

公开(公告)号：US20210295894A1

公开(公告)日：2021-09-23

申请号：US17238000

申请日：2021-04-22

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US10163485B2

公开(公告)日：2018-12-25

申请号：US15480382

申请日：2017-04-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G06F13/16 ,  G11C29/02

Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.

公开(公告)号：US10037952B2

公开(公告)日：2018-07-31

申请号：US15408683

申请日：2017-01-18

Applicant: MEDIATEK INC.

Inventor： Chun-Wei Chang ,  Shang-Pin Chen

IPC: H05K1/02 ,  H01L23/66 ,  H01L25/065 ,  H05K1/18 ,  H01L23/538 ,  H01L23/552 ,  G06F13/40 ,  H01L27/12 ,  H04B3/32 ,  H01L23/00 ,  H05K3/46

CPC classification number: H01L23/66 ,  G06F13/4072 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0655 ,  H01L27/12 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/3025 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/181 ,  H05K3/46 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/10318 ,  H05K2201/10522 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a printed circuit board (PCB), and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device of the PCB via the corresponding pins and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces of PCB via the corresponding pins. The conductive traces corresponding to the second driving units are separated by the conductive traces corresponding to the first driving units on the PCB.