公开(公告)号：US11949022B2

公开(公告)日：2024-04-02

申请号：US17678971

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L29/788 ,  H01L21/285 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/788 ,  H01L21/28518 ,  H01L23/535 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US11665893B2

公开(公告)日：2023-05-30

申请号：US15255967

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun Jeff Hu ,  Haitao Liu

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

公开(公告)号：US20230066753A1

公开(公告)日：2023-03-02

申请号：US17446649

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, a pillar comprising a channel material extending vertically through the stack, and a sense device comprising a gate material within the source tier. The gate material of the sense devices is in electrical communication with the channel material of the pillar. Related memory devices, systems, and methods are also described.

公开(公告)号：US20220262821A1

公开(公告)日：2022-08-18

申请号：US17661713

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Wei Yeeng Ng ,  James C. Brighten

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1157

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

公开(公告)号：US20210050362A1

公开(公告)日：2021-02-18

申请号：US16541944

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Wei Yeeng Ng ,  James C. Brighten

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

公开(公告)号：US10651315B2

公开(公告)日：2020-05-12

申请号：US13716287

申请日：2012-12-17

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157 ,  H01L21/285 ,  H01L23/535 ,  H01L29/66 ,  H01L29/792

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US20170075613A1

公开(公告)日：2017-03-16

申请号：US15342287

申请日：2016-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G06F12/0846

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract translation: 在存储器装置中，标志存储单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

公开(公告)号：US20250095746A1

公开(公告)日：2025-03-20

申请号：US18967011

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Carmine Miccoli ,  Andrew Bicksler

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to program the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of one or more programming pulses satisfies a condition. The first set voltage is adjusted to a second step voltage level in response to the condition being satisfied.

公开(公告)号：US20220181483A1

公开(公告)日：2022-06-09

申请号：US17678971

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/285 ,  H01L23/535

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US11289611B2

公开(公告)日：2022-03-29

申请号：US16845793

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L29/788 ,  H01L23/535 ,  H01L21/285 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/66

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.