公开(公告)号：US09767886B2

公开(公告)日：2017-09-19

申请号：US15093273

申请日：2016-04-07

Applicant: Micron Technology, Inc.

Inventor： Joo S Choi ,  Troy A. Manning ,  Brent Keeth

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

公开(公告)号：US09196313B2

公开(公告)日：2015-11-24

申请号：US14511794

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G11C5/02 ,  G11C5/06 ,  H01L23/12 ,  H01L23/48 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/20 ,  G11C2207/2227 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.

Abstract translation: 一些实施例包括具有布置在堆叠中的骰子的装置和方法。 骰子至少包括第一管芯和第二管芯，以及连接到管芯的连接。 连接可以被配置为在将第一标识分配给第一管芯期间将控制信息传送到第一管芯，并且在将第二标识分配给第二管芯期间将控制信息从第一管芯传送到第二管芯。

公开(公告)号：US09058875B2

公开(公告)日：2015-06-16

申请号：US13921951

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

公开(公告)号：US12243610B2

公开(公告)日：2025-03-04

申请号：US17821676

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/56

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

公开(公告)号：US12170127B2

公开(公告)日：2024-12-17

申请号：US18086991

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Brent Keeth ,  Matthew A. Prather

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/04

Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

公开(公告)号：US20240288925A1

公开(公告)日：2024-08-29

申请号：US18657379

申请日：2024-05-07

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G06F1/3225 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F1/3225 ,  G06F13/1678 ,  G06F13/409

Abstract: The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.

公开(公告)号：US20240194287A1

公开(公告)日：2024-06-13

申请号：US18525403

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C29/025

Abstract: Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.

公开(公告)号：US11893245B2

公开(公告)日：2024-02-06

申请号：US17863994

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0676 ,  G06F3/0679

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

公开(公告)号：US20220237077A1

公开(公告)日：2022-07-28

申请号：US17158874

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Brent Keeth

IPC: G06F11/10 ,  G06F11/07

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

公开(公告)号：US11281608B2

公开(公告)日：2022-03-22

申请号：US16058868

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  H01L23/538 ,  G06F13/16 ,  G06F3/06 ,  G06F12/1027 ,  H01L25/065 ,  H01L25/18

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.