公开(公告)号：US20200373252A1

公开(公告)日：2020-11-26

申请号：US16993860

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US10741528B2

公开(公告)日：2020-08-11

申请号：US16416625

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/552 ,  H01L23/48 ,  H01L25/00 ,  H01L23/04 ,  H01L23/36

Abstract: A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.

公开(公告)号：US20200219851A1

公开(公告)日：2020-07-09

申请号：US16823028

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L25/065 ,  H01L23/495 ,  H01L23/48 ,  H01L25/00 ,  H01L23/64 ,  H01L21/56 ,  H01L23/36

Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

公开(公告)号：US20200168517A1

公开(公告)日：2020-05-28

申请号：US16775163

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC: H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00

Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.

公开(公告)号：US20190279967A1

公开(公告)日：2019-09-12

申请号：US16416625

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/552 ,  H01L25/00

Abstract: A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.

公开(公告)号：US10043688B1

公开(公告)日：2018-08-07

申请号：US15867071

申请日：2018-01-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy E. Minnich ,  Brandon P. Wirz ,  Bret K. Street ,  James M. Derderian

IPC: B32B43/00 ,  H01L21/67 ,  H01L21/683

Abstract: An apparatus, system, and a method of using the apparatus or system that includes a bladder positioned between tape and an adhesive layer configured to selectively connect the tape to a semiconductor device. The bladder includes one or more chambers that may be selectively expanded to move a portion of the bladder and adhesive layer away from the tape, which may enable the removal of the semiconductor device. The flow of fluid into each of the chambers may selectively expand the chambers. The chambers may have a substantially rounded upper profile or a substantially pointed upper profile. A material within the chambers may be heated to expand the chambers. A plurality of conduits may permit the flow of fluid into the chambers. The conduits may be inserted into the bladder. The chambers may be collapsed after expansion to enable the removal of a semiconductor device from the tape.

公开(公告)号：US20160358898A1

公开(公告)日：2016-12-08

申请号：US14730681

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

Abstract translation: 制造半导体器件封装的方法可以包括将第一半导体管芯附接到载体晶片，第一半导体管芯的面向载体晶片的非活性表面。 一个或多个附加的半导体管芯可以在第一半导体管芯上与第一半导体管芯的与载体晶片相对的一侧堆叠以形成半导体管芯堆叠。 保护材料可以位于半导体管芯的堆叠之上，保护材料的一部分沿着第一半导体管芯的侧表面延伸到接近第一半导体管芯的非活性表面的位置。 载体晶片可以与第一半导体管芯分离。

公开(公告)号：US20250140756A1

公开(公告)日：2025-05-01

申请号：US19005309

申请日：2024-12-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

公开(公告)号：US12278202B2

公开(公告)日：2025-04-15

申请号：US17830224

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Bret K. Street ,  Debjit Datta ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/00

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

公开(公告)号：US20240071969A1

公开(公告)日：2024-02-29

申请号：US18220734

申请日：2023-07-11

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street ,  Bang-Ning Hsu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48229 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: Semiconductor devices and semiconductor device assemblies, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a support substrate, a first die package carried by the support substrate, and a second die package carried by the first die package. Each of the first and second die packages can include a first die, a second die hybrid bonded a surface of the first die, and a third die hybrid bonded to a surface of the second die. The first die is coupled to the third die via an interconnect portion of the second die. Further, the third die can include an array of active cells for each of the packages, the second die can include complementary-metal-oxide-semiconductor (CMOS) circuitry accessing the active cells, and the first die can include backend of line (BEOL) circuitry associated with the active cells and CMOS circuitry.