公开(公告)号：US09305659B2

公开(公告)日：2016-04-05

申请号：US14826298

申请日：2015-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

Abstract translation: 存储器件具有存储器单元的阵列和耦合到存储器单元阵列的控制器。 控制器被配置为在执行对存储器件执行的特定编程操作的一部分之后以及在执行对存储器件执行的特定编程操作的后续部分之后确定程序窗口。 控制器被配置为响应于由存储器单元的特定状态经历的程序干扰的量来确定程序窗口。 控制器被配置为使用所确定的程序窗口来执行在存储器设备上执行的特定编程操作的后续部分。

公开(公告)号：US09025388B2

公开(公告)日：2015-05-05

申请号：US14045492

申请日：2013-10-03

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Frankie Roohparvar ,  Giovanni Santin ,  Vishal Sarin ,  Allahyar Vahidimowlavi ,  Tommaso Vali

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C11/404

CPC classification number: G11C16/10 ,  G11C11/404 ,  G11C11/5628 ,  G11C16/3404

Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

公开(公告)号：US20150117111A9

公开(公告)日：2015-04-30

申请号：US13758379

申请日：2013-02-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Giovanni Santin

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/3454

Abstract: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.

Abstract translation: 公开了用于编程存储器单元和存储器件的方法。 一种用于编程的方法包括执行一组存储器单元的程序验证操作。 检测到一些潜在的CS2情况。 如果检测到的潜在CS2情况的数量大于阈值，则在随后的编程操作中使用针对CS2情况的编程补偿。

公开(公告)号：US08937836B2

公开(公告)日：2015-01-20

申请号：US14223734

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Giovanni Santin ,  Ercole Di Iorio

IPC: G11C16/04 ,  G11C16/12 ,  G11C5/14 ,  G11C16/08

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C16/08

Abstract: The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.

Abstract translation: 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选择的字线 的阵列驱动晶体管。

公开(公告)号：US20130188427A1

公开(公告)日：2013-07-25

申请号：US13790393

申请日：2013-03-08

Applicant: Micron Technology, Inc.

Inventor： Tommaso Vali ,  Violente Moschiano ,  Giovanni Santin

IPC: G11C16/26 ,  G11C16/06

CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/76 ,  G11C29/789 ,  G11C29/82 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.

公开(公告)号：US20190018733A1

公开(公告)日：2019-01-17

申请号：US16105305

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US09455043B2

公开(公告)日：2016-09-27

申请号：US15075768

申请日：2016-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

Abstract translation: 存储器件具有控制器。 控制器被配置为使得存储器件禁止对一组存储器单元进行编程。 控制器被配置为使存储器件施加编程脉冲来控制该组存储器单元的栅极。 控制器被配置为确定响应于编程脉冲的存储器单元组经历的干扰量。 控制器被配置为响应于干扰量来确定程序窗口。

公开(公告)号：US20150170755A9

公开(公告)日：2015-06-18

申请号：US14162278

申请日：2014-01-23

Applicant: Micron Technology, Inc.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati ,  Violante Moschiano

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C27/02 ,  G11C2211/5642 ,  G11C2211/5646

Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

Abstract translation: 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

公开(公告)号：US09007832B2

公开(公告)日：2015-04-14

申请号：US13758379

申请日：2013-02-04

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Giovanni Santin

IPC: G11C11/34 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/3454

Abstract: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.

Abstract translation: 公开了用于编程存储器单元和存储器件的方法。 一种用于编程的方法包括执行一组存储器单元的程序验证操作。 检测到一些潜在的CS2情况。 如果检测到的潜在CS2情况的数量大于阈值，则在随后的编程操作中使用针对CS2情况的编程补偿。

公开(公告)号：US20150085581A1

公开(公告)日：2015-03-26

申请号：US14554794

申请日：2014-11-26

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Giovanni Santin ,  Michele Incarnati

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.

Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括将信号施加到与存储器单元相关联的线，该信号是基于数字信息生成的。 该方法还可以包括当信号被施加到线路时，当数字信息具有第一值时，确定存储器单元的状态是否接近目标状态，并且确定存储器单元的状态是否已经达到目标 当数字信息具有第二值时状态。 描述包括附加存储器件和方法的其它实施例。