公开(公告)号：US20170132073A1

公开(公告)日：2017-05-11

申请号：US15414699

申请日：2017-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F11/1048 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0207 ,  G06F12/0646 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.

公开(公告)号：US09594676B2

公开(公告)日：2017-03-14

申请号：US14513880

申请日：2014-10-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

IPC: G11C11/00 ,  G06F12/06 ,  G11C16/04 ,  G11C16/10 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F11/1048 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0207 ,  G06F12/0646 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. At least one group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the first block of memory cells.

Abstract translation: 存储器设备具有多个可单独擦除的存储器单元块，以及控制器，被配置为配置包括一组或多组开销数据存储单元的第一配置中的第一存储单元块，并且配置存储器单元的第二块 包括一组或多组用户数据存储器单元和至少一组开销数据存储器单元的第二配置。 第一配置与第二配置不同。 存储器单元的第二块的至少一组开销数据存储单元包括与第一存储单元块的至少一组开销数据存储单元不同的存储容量。

公开(公告)号：US09442796B2

公开(公告)日：2016-09-13

申请号：US14629228

申请日：2015-02-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/23 ,  H03M13/35

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/005 ,  H03M13/235 ,  H03M13/2933 ,  H03M13/353 ,  H03M13/6362 ,  H03M13/6375

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.

Abstract translation: 装置和方法根据速率兼容代码（例如速率兼容卷积码（RPCC））将数据存储在非易失性固态存储装置中。 这种存储器件的示例是闪存器件。 数据最初可以进行块编码，用于纠错和检测。 块编码数据可进一步进行卷积编码。 卷积编码数据可以被打孔并存储在存储设备中。 穿孔减少了用于存储数据的内存量。 根据条件，打孔的量可以从无穿刺变化到相对高的穿刺量，以改变所提供的附加错误校正的量和使用的存储器的数量。 当从存储设备读取数据时，可以对穿孔的数据进行解码。

公开(公告)号：US20160004436A1

公开(公告)日：2016-01-07

申请号：US14718461

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： Peter Feeley ,  Robert N. Leibowitz ,  William H. Radke ,  Neal A. Galbo ,  Victor Y. Tsai

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/32

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/28 ,  G06F13/32 ,  G06F13/385 ,  G06F13/4282

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

公开(公告)号：US20150234704A1

公开(公告)日：2015-08-20

申请号：US14629228

申请日：2015-02-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke

IPC: G06F11/10 ,  H03M13/35 ,  H03M13/23 ,  G11C29/52 ,  H03M13/00

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/005 ,  H03M13/235 ,  H03M13/2933 ,  H03M13/353 ,  H03M13/6362 ,  H03M13/6375

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.

公开(公告)号：US20150063031A1

公开(公告)日：2015-03-05

申请号：US14538020

申请日：2014-11-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

公开(公告)号：US08966352B2

公开(公告)日：2015-02-24

申请号：US13680908

申请日：2012-11-19

Applicant: Micron Technology, Inc.

Inventor： William H. Radke

IPC: H03M13/03 ,  H03M13/00 ,  G06F11/10 ,  H03M13/29

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/005 ,  H03M13/235 ,  H03M13/2933 ,  H03M13/353 ,  H03M13/6362 ,  H03M13/6375

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.

Abstract translation: 装置和方法根据速率兼容代码（例如速率兼容卷积码（RPCC））将数据存储在非易失性固态存储装置中。 这种存储器件的示例是闪存器件。 数据最初可以进行块编码，用于纠错和检测。 块编码数据可进一步进行卷积编码。 卷积编码数据可以被打孔并存储在存储设备中。 穿孔减少了用于存储数据的内存量。 根据条件，打孔的量可以从无穿刺变化到相对高的穿刺量，以改变所提供的附加错误校正的量和使用的存储器的数量。 当从存储设备读取数据时，可以对穿孔的数据进行解码。

公开(公告)号：US20140281811A1

公开(公告)日：2014-09-18

申请号：US14269397

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Peter Feeley ,  Neal A. Galbo ,  James Cooke ,  Victor Y. Tsai ,  Robert N. Leibowitz ,  William H. Radke

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/2064 ,  G06F12/0246 ,  G11C29/52

Abstract: The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.

Abstract translation: 本公开包括固态设备中用于面向对象的存储器的方法，设备和系统。 在固态设备中面向对象存储器的方法的一个实施例包括以原子操作方式访问定义的一组数据作为单个对象，其中访问来自除主机之外的源。 该实施例还包括将定义的一组数据作为单个对象存储在多个固态存储器块中，如由固态存储器块的数量的固态设备的控制部件格式化。

公开(公告)号：US20140204693A1

公开(公告)日：2014-07-24

申请号：US14224543

申请日：2014-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

Abstract: In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.

Abstract translation: 在一个实施例中，有缺陷的存储器块被替换为非缺陷存储块，并且电压延迟校正被应用于基于无缺陷存储器的实际位置替换缺陷存储块的无缺陷存储器块 块。

公开(公告)号：US20140098614A1

公开(公告)日：2014-04-10

申请号：US14056713

申请日：2013-10-17

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3495

Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

Abstract translation: 本公开包括用于处理存储器件中的阈值电压变化的方法，装置和系统。 多个实施例包括具有耦合到阵列的感测电路的存储器单元阵列和控制电路。 控制电路被配置为确定与存储器单元相关联的阈值电压（Vts）的变化而不使用参考单元，并且基于所确定的变化并且不使用参考单元来调整感测电路。