公开(公告)号：US20240304264A1

公开(公告)日：2024-09-12

申请号：US18180874

申请日：2023-03-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Chih-Chang Hsieh

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3481 ,  G11C16/102 ,  G11C16/26

Abstract: A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

公开(公告)号：US20240170046A1

公开(公告)日：2024-05-23

申请号：US17988760

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C11/408 ,  G11C11/4074

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4087

Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

公开(公告)号：US11374018B2

公开(公告)日：2022-06-28

申请号：US16931598

申请日：2020-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11529

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

公开(公告)号：US11257836B2

公开(公告)日：2022-02-22

申请号：US16782953

申请日：2020-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yu-Wei Jiang

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.

公开(公告)号：US10910402B1

公开(公告)日：2021-02-02

申请号：US16657810

申请日：2019-10-18

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yu-Wei Jiang

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/51

Abstract: A three-dimensional AND type flash memory and a manufacturing method thereof includes steps below is provided. A stack structure includes a first insulating layer and a first sacrificial layer is formed. A first pillar structure through the stack structure includes a second insulating layer and a second sacrificial layer surrounded by thereof is formed. A second pillar structure through the stack structure includes a channel layer and an insulating pillar surrounded by thereof is formed. The second sacrificial layer is located on both sides of the channel layer. The first sacrificial layer is removed. A lateral opening exposing a portion of the second insulating layer and the channel layer is formed. A gate insulating layer surrounding the exposed second insulating layer and channel layer is formed in the lateral opening. A gate layer is filled in the lateral opening. A conductive layer is used to replace the second sacrificial layer.

公开(公告)号：US20190371804A1

公开(公告)日：2019-12-05

申请号：US15996617

申请日：2018-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue

IPC: H01L27/11556 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

公开(公告)号：US09536573B2

公开(公告)日：2017-01-03

申请号：US14645446

申请日：2015-03-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L29/49 ,  G11C5/06 ,  G11C8/10 ,  H01L23/528 ,  H01L21/768 ,  H01L27/115

CPC classification number: G11C5/063 ,  G11C8/10 ,  G11C8/14 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/11548 ,  H01L27/11575

Abstract: A 3D memory structure and a method for manufactured the same are provided. The 3D memory structure comprises a plurality of strings, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of third conductive lines. The strings are disposed in parallel. The first conductive lines are disposed over the strings. Center regions of the first conductive lines are disposed perpendicular to the strings. The second conductive lines are disposed over the first conductive lines. The second conductive lines connect end regions of half of the first conductive lines. The third conductive lines are disposed over the second conductive lines. The third conductive lines connect end regions of the other half of the first conductive lines.

Abstract translation: 提供了3D存储器结构及其制造方法。 3D存储器结构包括多个串，多个第一导线，多个第二导线和多个第三导线。 琴弦平行放置。 第一导线设置在弦上。 第一导线的中心区域垂直于弦线设置。 第二导线设置在第一导线上。 第二导线连接一半第一导线的端部区域。 第三导线设置在第二导线上。 第三导线连接第一导电线的另一半的端部区域。

公开(公告)号：US09461064B2

公开(公告)日：2016-10-04

申请号：US14948482

申请日：2015-11-23

Applicant: Macronix International Co., Ltd

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

IPC: H01L21/82 ,  H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

公开(公告)号：US09245603B2

公开(公告)日：2016-01-26

申请号：US14058328

申请日：2013-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: G11C7/14 ,  H01L27/115

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

公开(公告)号：US20150357341A1

公开(公告)日：2015-12-10

申请号：US14296173

申请日：2014-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

IPC: H01L27/115 ,  H01L29/40

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

Abstract translation: 存储器阵列包括沿着第一方向延伸的多个脊形多层堆叠，以及形成在所述多个脊形多层堆叠的顶部上的硬掩模层。 硬掩模层分别包括与多个脊形多层堆叠垂直对准的多个条带，沿着与第一方向正交的第二方向连接相邻条纹的多个桥，以及多个硬 通过多个桥和多个条之间的孔掩模。