公开(公告)号：US11594277B2

公开(公告)日：2023-02-28

申请号：US17871811

申请日：2022-07-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094

Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US20220359003A1

公开(公告)日：2022-11-10

申请号：US17871811

申请日：2022-07-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G11C11/408 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/4094

Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US20190034118A1

公开(公告)日：2019-01-31

申请号：US15662348

申请日：2017-07-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

Abstract: A data management method for a memory device includes: counting a system time; when at least a part of a block of the memory device is accessed or refreshed or programmed at first time, assigning a block number of the block to point to a maximum remaining retention time; when a first downgrade trigger time reaches, assigning the block number to point from the maximum remaining retention time to a medium remaining retention time; when a second downgrade trigger time reaches, assigning the block number to point from the medium remaining retention time to a minimum remaining retention time; and once the block number points to the minimum remaining retention time, refreshing the block and assigning the block number to point to the maximum remaining retention time.

公开(公告)号：US09734912B2

公开(公告)日：2017-08-15

申请号：US15208175

申请日：2016-07-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun Li ,  Yu-Ming Chang ,  Ping-Hsien Lin ,  Hsiang-Pang Li

IPC: G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5634 ,  G11C2211/5641

Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.

公开(公告)号：US09672067B2

公开(公告)日：2017-06-06

申请号：US14696657

申请日：2015-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ye-Jyun Lin ,  Hsiang-Pang Li ,  Shang-Xuan Zou ,  Chia-Lin Yang

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/4812

Abstract: A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.

公开(公告)号：US20170147217A1

公开(公告)日：2017-05-25

申请号：US15093841

申请日：2016-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Yu-Ming Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/10

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

公开(公告)号：US09478288B1

公开(公告)日：2016-10-25

申请号：US14687998

申请日：2015-04-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pang Li ,  Yu-Ming Chang

IPC: G11C16/04 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract translation: 一种用于编程存储器件的方法包括以下步骤：执行交织编程，包括：在第一时间间隔期间对第一存储器单元进行编程，并在第二时间间隔内相应地验证第一存储器单元; 在第三时间间隔期间编程第二存储器单元，并在第一和第二时间间隔之间的第四时间间隔期间相应地验证第二存储器单元; 以及在所述第一和第二时间间隔之间插入至少一个虚拟周期，以确保所述第一存储单元的每单位时间的电阻变化小于阈值。

公开(公告)号：US20160307627A1

公开(公告)日：2016-10-20

申请号：US14687998

申请日：2015-04-16

Applicant: Macronix International Co., Ltd.

Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pang Li ,  Yu-Ming Chang

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract translation: 一种用于编程存储器件的方法包括以下步骤：执行交织编程，包括：在第一时间间隔期间对第一存储器单元进行编程，并在第二时间间隔内相应地验证第一存储器单元; 在第三时间间隔期间编程第二存储器单元，并在第一和第二时间间隔之间的第四时间间隔期间相应地验证第二存储器单元; 以及在所述第一和第二时间间隔之间插入至少一个虚拟周期，以确保所述第一存储单元的每单位时间的电阻变化小于阈值。

公开(公告)号：US20160154593A1

公开(公告)日：2016-06-02

申请号：US14811970

申请日：2015-07-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Chun-Ta Lin ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0641

Abstract: A memory system is provided. The memory system includes a memory controller and a first memory block. The first memory block is configured to store a first data from a top of the first memory block in a top-down fashion. The first memory block is configured to store a first metadata corresponding to the first data from a bottom of the first memory block in a bottom-up fashion. The first data forms a first data area. The first metadata forms a first metadata area. And a first continuous space is formed between a bottom of the first data area and a top of the first metadata area.

Abstract translation: 提供了一种存储系统。 存储器系统包括存储器控制器和第一存储器块。 第一存储块被配置为以自顶向下的方式存储来自第一存储器块的顶部的第一数据。 第一存储器块被配置为以自下而上的方式存储来自第一存储器块的底部的与第一数据相对应的第一元数据。 第一数据形成第一数据区。 第一个元数据形成第一个元数据区域。 并且在第一数据区域的底部和第一元数据区域的顶部之间形成第一连续空间。

公开(公告)号：US20150149867A1

公开(公告)日：2015-05-28

申请号：US14276002

申请日：2014-05-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ren-Shuo Liu ,  Meng-Yen Chuang ,  Chia-Lin Yang ,  Cheng-Hsuan Li ,  Kin-Chu Ho ,  Hsiang-Pang Li

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1016

Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Abstract translation: 提供了一种存储装置的操作方法。 操作方法包括以下步骤。 首先，从第一存储单元的目标地址读取第一数据。 然后，辅助单元检查目标地址是否对应于存储在第二存储单元中的第二数据。 如果目标地址对应于第二数据，则辅助单元根据第二数据更新第一数据以产生更新的数据。 接下来，纠错码（ECC）对更新后的数据进行解码处理，生成译码后的数据。