公开(公告)号：US20060273414A1

公开(公告)日：2006-12-07

申请号：US11465219

申请日：2006-08-17

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC分类号： H01L29/94

CPC分类号： H01L21/823842 ,  H01L29/4958

摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

公开(公告)号：US20060246716A1

公开(公告)日：2006-11-02

申请号：US11118237

申请日：2005-04-29

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC分类号： H01L21/4763

CPC分类号： H01L21/823857 ,  H01L27/11

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成第一氧化物层。 第一氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。

公开(公告)号：US20050136679A1

公开(公告)日：2005-06-23

申请号：US10745449

申请日：2003-12-22

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L29/51 ,  H01L21/302

CPC分类号： H01L21/28194 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31608 ,  H01L21/3185 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  Y10S438/91 ,  Y10S438/954

摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

摘要翻译： 本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。 以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

公开(公告)号：US20050136632A1

公开(公告)日：2005-06-23

申请号：US10738957

申请日：2003-12-17

申请人： Antonio Rotondaro ,  Mark Visokay ,  James Chambers ,  Luigi Colombo

发明人： Antonio Rotondaro ,  Mark Visokay ,  James Chambers ,  Luigi Colombo

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.

摘要翻译： 公开了通过制造具有在半导体器件的不同区域中具有可选厚度的栅极电介质的晶体管器件来促进半导体制造的方法和系统。 厚度对应于相应的晶体管器件的工作电压。 此外，本发明还提供了可以制造具有高k电介质材料的栅极电介质的系统和方法，其允许比常规二氧化硅更厚的栅极电介质。

公开(公告)号：US20050130442A1

公开(公告)日：2005-06-16

申请号：US10734708

申请日：2003-12-11

申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/02148 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3162 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/518

摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。

公开(公告)号：US20050124109A1

公开(公告)日：2005-06-09

申请号：US10726987

申请日：2003-12-03

申请人： Manuel Quevedo-Lopez ,  James Chambers ,  Luigi Colombo ,  Mark Visokay

发明人： Manuel Quevedo-Lopez ,  James Chambers ,  Luigi Colombo ,  Mark Visokay

IPC分类号： C23C16/40 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/302 ,  H01L21/461 ,  H01L21/8242 ,  H01L21/31

CPC分类号： H01L21/0234 ,  C23C16/401 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/31691

摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.

摘要翻译： 具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。

公开(公告)号：US20050136589A1

公开(公告)日：2005-06-23

申请号：US10738958

申请日：2003-12-17

申请人： Antonio Rotondaro ,  Douglas Mercer ,  Luigi Colombo ,  Mark Visokay ,  Haowen Bu ,  Malcolm Bevan

发明人： Antonio Rotondaro ,  Douglas Mercer ,  Luigi Colombo ,  Mark Visokay ,  Haowen Bu ,  Malcolm Bevan

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/28176 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

摘要翻译： 公开了制造具有高k电介质层的半导体器件的方法。 本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染 工具 封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。 结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

公开(公告)号：US20050101145A1

公开(公告)日：2005-05-12

申请号：US10703388

申请日：2003-11-06

申请人： Mark Visokay ,  Luigi Colombo

发明人： Mark Visokay ,  Luigi Colombo

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

摘要翻译： 制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。 将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。 掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。 多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。 蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

公开(公告)号：US07531400B2

公开(公告)日：2009-05-12

申请号：US11556480

申请日：2006-11-03

申请人： Mark Visokay ,  Luigi Colombo

发明人： Mark Visokay ,  Luigi Colombo

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/823835

摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.

摘要翻译： 提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。 上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在 上下金属硅化物。 可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入掺杂下硅化物。

公开(公告)号：US20070059872A1

公开(公告)日：2007-03-15

申请号：US11556480

申请日：2006-11-03

申请人： Mark Visokay ,  Luigi Colombo

发明人： Mark Visokay ,  Luigi Colombo

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823835

摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.

摘要翻译： 提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。 上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在 上下金属硅化物。 可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入掺杂下硅化物。