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    SEMICONDUCTOR MEMORY DEVICE
    22.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110051489A1

    公开(公告)日：2011-03-03

    申请号：US12942627

    申请日：2010-11-09

    申请人： Naoki Kuroda ,  Yoshinobu Yamagami

    发明人： Naoki Kuroda ,  Yoshinobu Yamagami

    IPC分类号： G11C5/06

    CPC分类号： G11C11/412 ,  G11C8/16

    摘要： A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.

    摘要翻译： 半导体存储器件包括第一反相器和第二反相器，每个具有输入和输出，第一和第二反相器的每一个的输出连接到另一个的输入，以便存储数据; CMOS开关，被配置为连接 第一反相器的输入和写入位线，具有连接到第一反相器的输出的栅极的读取MOS晶体管和被配置为将读取的MOS晶体管连接到读取位线的MOS开关。 第一和第二逆变器具有不同的尺寸并连接到不同的源电源。

    Semiconductor integrated circuit
    23.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20070253125A1

    公开(公告)日：2007-11-01

    申请号：US11730683

    申请日：2007-04-03

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： H02H7/00

    CPC分类号： G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/1201

    摘要： A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

    摘要翻译： 包括在单个芯片上的多个电路块的半导体集成电路和用于向多个电路块传送公共电源电压的多个内部电源电路包括：用于连接多个电路块的共享电源互连和 多个内部电源电路; 以及连接到共享电源互连的外部焊盘。 每个内部电源电路的输出电源电压是否由一定的电源控制信号控制。

    Semiconductor memory device and test method thereof
    24.
    发明授权
    Semiconductor memory device and test method thereof 失效
    半导体存储器件及其测试方法

    公开(公告)号：US06909624B2

    公开(公告)日：2005-06-21

    申请号：US10624890

    申请日：2003-07-23

    申请人： Hiroyuki Sadakata ,  Naoki Kuroda

    发明人： Hiroyuki Sadakata ,  Naoki Kuroda

    IPC分类号： G01R31/28 ,  G11C29/26 ,  G11C29/34 ,  G11C5/06

    CPC分类号： G11C29/56004 ,  G11C29/26 ,  G11C2029/0401 ,  G11C2029/1806 ,  G11C2029/2602

    摘要： In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested using the same test pattern (for example, HALF-MARCH) even if a special pin is provided for each RAM, because X, Y address mapping differs between the different RAMs; accordingly, the test has to be performed by dividing the RAMs into groups each consisting of RAMs having the same memory space, and this has lead to increased test time. An external address signal and a test-only address signal are provided as RAM control signals and, in the latter case, the number of X, Y addresses in each of the RAMs 4 and 5 is set equal to that of the largest capacity RAM 3 within the same chip, thereby making the X, Y address mapping the same for all the RAMs 3 to 5.

    摘要翻译： 在近来的系统LSI中，根据系统侧的需要，将单个芯片上的容量和位宽不同的多个RAM进行安装。 然而，当测试多个RAM时，如果RAM的容量不同，即使为每个RAM提供特殊引脚，也不能使用相同的测试模式（例如，HALF-MARCH）进行测试，因为X，Y地址映射 不同的RAM之间有所不同; 因此，必须通过将RAM分成由具有相同存储空间的RAM组成的组来执行测试，并且这导致增加的测试时间。 提供外部地址信号和仅测试地址信号作为RAM控制信号，并且在后一种情况下，每个RAM4和5中的X，Y地址的数量被设置为等于最大容量RAM 3的数量 在同一个芯片内，从而使X，Y地址映射对于所有RAM3至5都是相同的。

    Power control for a plurality of internal power supply circuits of a semiconductor integrated circuit
    26.
    发明授权
    Power control for a plurality of internal power supply circuits of a semiconductor integrated circuit 有权
    用于半导体集成电路的多个内部电源电路的功率控制

    公开(公告)号：US07779277B2

    公开(公告)日：2010-08-17

    申请号：US11730683

    申请日：2007-04-03

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G06F1/00 ,  G11C29/00 ,  H02J1/00

    CPC分类号： G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/1201

    摘要： A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

    摘要翻译： 包括在单个芯片上的多个电路块的半导体集成电路和用于向多个电路块传送公共电源电压的多个内部电源电路包括：用于连接多个电路块的共享电源互连和 多个内部电源电路; 以及连接到共享电源互连的外部焊盘。 每个内部电源电路的输出电源电压是否由一定的电源控制信号控制。

    Semiconductor memory device
    27.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07330386B2

    公开(公告)日：2008-02-12

    申请号：US11491934

    申请日：2006-07-25

    申请人： Naoki Kuroda ,  Masanobu Hirose

    发明人： Naoki Kuroda ,  Masanobu Hirose

    IPC分类号： G11C7/00

    CPC分类号： G11C17/12 ,  G11C2207/2227

    摘要： In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

    摘要翻译： 在存储单元阵列中，提供源极线，使得源极线中的每一个连接到属于相邻两行的存储单元中的每一个，以及用于提供高于地的源极偏置电位的多个源极偏置控制电路 提供电位并且低于电源电位以分别对应于源极线。 在待机期间，每个源极线被控制为处于源极偏置电位被提供的状态，并且在有效周期期间，一个或多个不连接到存储器单元之一的源极线 被读取的数据被控制为处于提供源极偏置电位的状态。

    Semiconductor memory device
    28.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20070030744A1

    公开(公告)日：2007-02-08

    申请号：US11487976

    申请日：2006-07-18

    申请人： Toshihiro Nakamura ,  Naoki Kuroda ,  Masanobu Hirose

    发明人： Toshihiro Nakamura ,  Naoki Kuroda ,  Masanobu Hirose

    IPC分类号： G11C7/00

    CPC分类号： H01L27/0207 ,  H01L27/105

    摘要： Source potential connection transistors, each supplying a source control potential from a source potential wiring to a source node, are disposed so as to be dispersed in a memory cell array. In addition, a source potential control circuit is disposed inside a row decoder block. With this configuration, the number of the cells connected to each word line can be increased, and the area of the memory core can be reduced. Furthermore, the pattern shape of the diffusion layer constituting the source potential connection transistor is made the same as that of the diffusion layer of a memory cell transistor, whereby mask creation can be facilitated.

    摘要翻译： 源电位连接晶体管，每个源极控制电位从源极布线提供到源极节点，以分散在存储单元阵列中。 此外，源电位控制电路设置在行解码器块内。 利用这种配置，可以增加连接到每个字线的单元的数量，并且可以减小存储器核心的面积。 此外，构成源极电位连接晶体管的扩散层的图案形状与存储单元晶体管的扩散层的图案形状相同，从而可以促进掩模创建。

    Semiconductor memory device
    29.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060250869A1

    公开(公告)日：2006-11-09

    申请号：US11484756

    申请日：2006-07-12

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1048 ,  G11C2207/002

    摘要： A semiconductor memory device 1 comprises precharge circuits 31, 32 corresponding to global data line pairs DL0/NDL0, DL1/NDL1, but not a precharge circuit corresponding to a local data line pair LDL/NLDL. In a command waiting state, data line selection switches 21, 22 are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches 21, 22, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

    摘要翻译： 半导体存储器件1包括对应于全局数据线对DL 0 / NDL 0，DL 1 / NDL 1的预充电电路31,32，而不是与本地数据线对LDL / NLDL相对应的预充电电路。 在命令等待状态下，数据线选择开关21,22被控制为处于连接状态，使得本地数据线对和全局数据线对在一起被彼此连接的同时被预充电。 在命令执行状态下，命令执行不需要的数据线选择开关21,22之一处于打开状态。 类似地，可以提供仅包括对应于本地数据线对的预充电电路的半导体存储器件。

    Semiconductor integrated circuit device
    30.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050201193A1

    公开(公告)日：2005-09-15

    申请号：US11074897

    申请日：2005-03-09

    申请人： Naoki Kuroda ,  Yuji Nakai

    发明人： Naoki Kuroda ,  Yuji Nakai

    IPC分类号： G06F12/00 ,  G06F12/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063

    CPC分类号： G11C7/10 ,  G11C7/1006 ,  G11C2207/107

    摘要： A plurality of logic circuits both access the DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

    摘要翻译： 多个逻辑电路都通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。 来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。