公开(公告)号：US20080142873A1

公开(公告)日：2008-06-19

申请号：US11611856

申请日：2006-12-16

申请人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

发明人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

摘要翻译： 提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层 该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

公开(公告)号：US06864556B1

公开(公告)日：2005-03-08

申请号：US10335445

申请日：2002-12-31

申请人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

发明人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

IPC分类号： G03F7/09 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/47 ,  H01L31/0232

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0332 ,  H01L21/28123 ,  H01L29/785

摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

摘要翻译： 采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形 形成在可图案层中。 有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。 有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

公开(公告)号：US06797552B1

公开(公告)日：2004-09-28

申请号：US10299434

申请日：2002-11-19

申请人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

发明人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.

摘要翻译： 使用双层硬掩模结构各向异性地图案化材料层。 在用于图案化双层硬掩模的上层的光致抗蚀剂掩模的残余光致抗蚀剂在图案化多晶硅层之前被去除。 在图案化材料层之后，钝化剂随后从外部源引入。 这提供了当被蚀刻时材料层的所有部分基本上均匀地供应钝化剂，而不是依赖于在蚀刻期间消除光致抗蚀剂的钝化剂的产生，这可以产生钝化剂可用性的局部不均匀性 由于在不同尺寸的特征上残留的光刻胶厚度的差异。

公开(公告)号：US06753247B1

公开(公告)日：2004-06-22

申请号：US10285183

申请日：2002-10-31

申请人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

发明人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

IPC分类号： H01L214763

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L27/285

摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.

摘要翻译： 公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。 将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。 然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。 然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。 根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线 电介质材料，使得顶部电极通过通孔连接到字线。

公开(公告)号：US06610580B1

公开(公告)日：2003-08-26

申请号：US09563179

申请日：2000-05-02

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/11517

摘要： In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

摘要翻译： 在本发明的第一方面，公开了一种闪存阵列。 闪存阵列包括包含有源区的衬底，其中有源区由氮化物层限定，氮化物层包括顶表面。 闪存阵列还包括衬底中的浅沟槽，每个浅沟槽包括一层氧化物，氧化层具有顶表面，其中氧化层的顶表面和氮化层的顶表面 在基本相同的平面和通道区域上，其中通道区域中多边形桁条的出现被大大减少。 在本发明的第二方面中，公开了一种用于制造闪存阵列的方法和系统。 该方法包括以下步骤：在衬底上提供氮化物层，在衬底中形成沟槽，然后在沟槽中生长一层氧化物。 最后，氧化层被抛光。 通过使用本发明的优选实施例，与LOCOS工艺相反，实现了浅沟槽隔离工艺，从而减少了通道区域中多边形的发生。 因此，相邻区域之间不需要的电短路径的发生显着减少。

公开(公告)号：US06566230B1

公开(公告)日：2003-05-20

申请号：US10032630

申请日：2001-12-27

申请人： Harpreet K. Sachar ,  Unsoon Kim ,  Mark S. Chang ,  Chih Y. Yang ,  Jayendra D. Bhakta

发明人： Harpreet K. Sachar ,  Unsoon Kim ,  Mark S. Chang ,  Chih Y. Yang ,  Jayendra D. Bhakta

IPC分类号： H03L2176

CPC分类号： H01L21/76224

摘要： A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

摘要翻译： 公开了一种用于在半导体器件制造期间执行沟槽隔离的方法。 该方法包括图案化硬掩模以限定衬底上的有源区和隔离区，以及沿着硬掩模的边缘形成间隔物。 然后使用间隔件作为掩模在衬底中形成沟槽，从而增加衬底在有源区域下的宽度并增加器件的Weff。

公开(公告)号：US6124201A

公开(公告)日：2000-09-26

申请号：US097126

申请日：1998-06-12

申请人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

发明人： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76802

摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

摘要翻译： 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

公开(公告)号：US08507969B2

公开(公告)日：2013-08-13

申请号：US13465649

申请日：2012-05-07

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻穿过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US06878961B2

公开(公告)日：2005-04-12

申请号：US10951370

申请日：2004-09-28

申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Mark S. Chang

发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Mark S. Chang

IPC分类号： G11C11/56 ,  G11C13/02 ,  H01L27/28 ,  H01L35/24

CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C13/04 ,  Y10S977/943

摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.

摘要翻译： 公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。 可控导电介质包含含有光敏化合物的有机半导体层。 使用图案化技术将有机半导体层形成为存储单元。

公开(公告)号：US06806165B1

公开(公告)日：2004-10-19

申请号：US10120116

申请日：2002-04-09

申请人： Dawn M. Hopper ,  Minh V. Ngo ,  Mark S. Chang

发明人： Dawn M. Hopper ,  Minh V. Ngo ,  Mark S. Chang

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of between 100 and 400 Angstroms, and preferably 200 Angstroms. Depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of defects at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.

摘要翻译： 公开了一种在半导体制造过程中填充隔离沟槽结构的方法。 该方法包括两步沉积工艺，其包括在沟槽表面上沉积富硅衬垫，然后用偏压的高密度等离子体沉积工艺用氧化物填充隔离沟槽。 在优选的实施方案中，富硅衬里是厚度为100至400埃，优选为200埃的原位HDP衬垫。 在沉积高密度等离子体氧化物之前，在沟槽表面上沉积富硅衬层消除了在隔离沟槽结构表面形成缺陷。 因此，提高了氧化物填充的质量，以及产量和器件性能。