公开(公告)号：US06566230B1

公开(公告)日：2003-05-20

申请号：US10032630

申请日：2001-12-27

申请人： Harpreet K. Sachar ,  Unsoon Kim ,  Mark S. Chang ,  Chih Y. Yang ,  Jayendra D. Bhakta

发明人： Harpreet K. Sachar ,  Unsoon Kim ,  Mark S. Chang ,  Chih Y. Yang ,  Jayendra D. Bhakta

IPC分类号： H03L2176

CPC分类号： H01L21/76224

摘要： A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.

摘要翻译： 公开了一种用于在半导体器件制造期间执行沟槽隔离的方法。 该方法包括图案化硬掩模以限定衬底上的有源区和隔离区，以及沿着硬掩模的边缘形成间隔物。 然后使用间隔件作为掩模在衬底中形成沟槽，从而增加衬底在有源区域下的宽度并增加器件的Weff。

公开(公告)号：US07439141B2

公开(公告)日：2008-10-21

申请号：US10277395

申请日：2002-10-22

申请人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

发明人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

IPC分类号： H01L21/00

CPC分类号： H01L21/76235

摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

摘要翻译： 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。 该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

公开(公告)号：US06670691B1

公开(公告)日：2003-12-30

申请号：US10174550

申请日：2002-06-18

申请人： Harpreet K. Sachar ,  Unsoon Kim ,  Jack F. Thomas

发明人： Harpreet K. Sachar ,  Unsoon Kim ,  Jack F. Thomas

IPC分类号： H01L2900

CPC分类号： H01L21/76229

摘要： A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

摘要翻译： 公开了一种用于在半导体制造工艺期间填充窄隔离沟槽的方法。 半导体包括形成在基板的芯区域中的高纵横比窄隔离沟槽和形成在基板的电路区域中的宽隔离沟槽。 在沟槽形成之后，在其中生长热氧化层的厚度足以完全填充高纵横比窄隔离沟槽的所有隔离沟槽中进行厚衬层氧化。 在衬里氧化之后，宽隔离沟槽填充有隔离电介质，由此所有沟槽均匀地填充有最小的空隙。

公开(公告)号：US07985687B1

公开(公告)日：2011-07-26

申请号：US11186969

申请日：2005-07-22

申请人： Angela T. Hui ,  Hiroyuki Kinoshita ,  Unsoon Kim ,  Harpreet K. Sachar

发明人： Angela T. Hui ,  Hiroyuki Kinoshita ,  Unsoon Kim ,  Harpreet K. Sachar

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76232 ,  H01L27/11521 ,  H01L27/11568

摘要： A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.

摘要翻译： 一种用于形成存储器件的方法包括在衬底上形成硬掩模，其中硬掩模包括形成在第一掩模层上的第一掩模层和第二掩模层。 蚀刻衬底以形成沟槽。 沟槽填充有场氧化物材料。 使用第一蚀刻技术从存储器件剥离第二掩模层，并且使用第二蚀刻技术将第一掩模层从存储器件剥离，其中第二蚀刻技术不同于第一蚀刻技术。

公开(公告)号：US06509232B1

公开(公告)日：2003-01-21

申请号：US09969573

申请日：2001-10-01

申请人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

发明人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.

摘要翻译： 形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。 核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。 核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。 电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的 。 沉积沟槽电介质材料以填充STI开口。 此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。 外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。 核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

公开(公告)号：US08802537B1

公开(公告)日：2014-08-12

申请号：US11189874

申请日：2005-07-27

申请人： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

发明人： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/02057

摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。 在沟槽的相对侧上修整氮化物层。 在沟槽中形成衬里氧化物层。

公开(公告)号：US08742486B2

公开(公告)日：2014-06-03

申请号：US11702846

申请日：2007-02-05

申请人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

发明人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

IPC分类号： H01L29/68

CPC分类号： H01L29/792 ,  H01L21/823418 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在半导体衬底中的第一沟槽和形成在与所述第一沟槽相邻的所述半导体衬底中的第二沟槽。 第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁。 存储单元还包括形成在第一沟槽的第一侧壁上的第一存储元件和形成在第二沟槽的第二侧壁上的第二存储元件。

公开(公告)号：US07307002B2

公开(公告)日：2007-12-11

申请号：US11099339

申请日：2005-04-04

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

IPC分类号： H01L21/76

CPC分类号： H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

摘要翻译： 公开了一种用于在半导体晶片中定义多晶硅层的方法。 使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。 使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

公开(公告)号：US06924220B1

公开(公告)日：2005-08-02

申请号：US09922536

申请日：2001-08-03

申请人： Kai Yang ,  John Jianshi Wang ,  Unsoon Kim

发明人： Kai Yang ,  John Jianshi Wang ,  Unsoon Kim

IPC分类号： H01L21/321 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/3201

CPC分类号： H01L27/11526 ,  H01L21/3212 ,  H01L27/105 ,  H01L27/11531

摘要： A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory circuits. In one aspect, the protective mask is formed over a substantial area of the Peripheral region. In another aspect, the protective mask is formed over a substantial area of an active part of the peripheral region.

摘要翻译： 一种通过在多晶硅抛光期间在周边区域上形成保护掩模来保护外围区域的方法，同时在闪速存储器电路中形成自对准的多晶硅栅极。 在一个方面，保护掩模形成在外围区域的大部分区域上。 另一方面，保护掩模形成在周边区域的有效部分的实质区域上。

公开(公告)号：US06444530B1

公开(公告)日：2002-09-03

申请号：US09318429

申请日：1999-05-25

申请人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

发明人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  Y10T428/12542 ,  Y10T428/1259 ,  Y10T428/12625 ,  Y10T428/12778 ,  H01L2924/00

摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

摘要翻译： 在闪速存储器件中形成触点的方法利用局部互连处理技术。 局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。 接触可以包括钨。 堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。