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    SILVER SELENIDE FILM STOICHIOMETRY AND MORPHOLOGY CONTROL IN SPUTTER DEPOSITION
    22.
    发明申请
    SILVER SELENIDE FILM STOICHIOMETRY AND MORPHOLOGY CONTROL IN SPUTTER DEPOSITION 有权
    溅射沉积物中的银塞子薄膜沉积和形态学控制

    公开(公告)号：US20140224646A1

    公开(公告)日：2014-08-14

    申请号：US14253649

    申请日：2014-04-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jiutao Li ,  Keith Hampton ,  Allen McTeer

    IPC: C23C14/06

    CPC classification number: H01L21/02631 ,  C23C14/0021 ,  C23C14/0623 ,  C23C14/3407 ,  C23C14/3492 ,  C23C14/548 ,  H01L21/02266 ,  Y10S428/938 ,  Y10T428/12896

    Abstract: A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr.

    Abstract translation: 溅射沉积硒化银并控制溅射沉积的硒化银膜的化学计量和结节缺陷形成的方法。 该方法包括使用溅射沉积工艺在约0.3mTorr至约10mTorr的压力下沉积硒化银。 根据本发明的一个方面，RF溅射沉积工艺可以优选地在约2mTorr至约3mTorr的压力下使用。 根据本发明的另一方面，脉冲DC溅射沉积工艺可优选地在约4mTorr至约5mTorr的压力下使用。

    Methods of Forming Doped Regions in Semiconductor Substrates
    23.
    发明申请
    Methods of Forming Doped Regions in Semiconductor Substrates 有权
    在半导体衬底中形成掺杂区域的方法

    公开(公告)号：US20130072006A1

    公开(公告)日：2013-03-21

    申请号：US13674674

    申请日：2012-11-12

    Applicant: Micron Technology, Inc.

    Inventor： Lequn Jennifer Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/223

    CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

    Abstract translation: 一些实施例包括在半导体衬底中形成一个或多个掺杂区域的方法。 可以使用等离子体掺杂来形成第一掺杂剂到衬底内的第一深度。 然后可以用第二掺杂剂冲击第一掺杂剂以将第一掺杂剂敲入衬底内的第二深度。 在一些实施方案中，第一掺杂剂是p型（例如硼），第二掺杂剂是中性型（例如锗）。 在一些实施方案中，第二掺杂剂比第一掺杂剂重。

    Integrated structures and methods of forming integrated structures
    25.
    发明授权
    Integrated structures and methods of forming integrated structures 有权

    公开(公告)号：US11107823B2

    公开(公告)日：2021-08-31

    申请号：US16684515

    申请日：2019-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L27/11524 ,  H01L21/02 ,  H01L21/322 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

    Semiconductor devices
    26.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09530842B2

    公开(公告)日：2016-12-27

    申请号：US14597766

    申请日：2015-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L29/76 ,  H01L29/08 ,  H01L29/45 ,  H01L21/223 ,  H01L27/092

    CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/823418 ,  H01L27/092 ,  H01L29/456 ,  H01L29/665

    Abstract: Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. Some embodiments include a method in which first boron-enhanced regions are formed within upper portions of n-type source/drain regions of an NMOS (n-type metal-oxide-semiconductor) device and second boron-enhanced regions are simultaneously formed within upper portions of p-type source/drain regions of a PMOS (p-type metal-oxide-semiconductor) device. The first and second boron-enhanced regions extend to depths of less than or equal to about 10 nanometers.

    Abstract translation: 一些实施例包括具有n型扩散区的器件，并且在n型扩散区内具有硼掺杂区。 硼掺杂区从n型扩散区的上表面延伸不超过约10纳米。 一些实施例包括其中在NMOS（n型金属氧化物半导体）器件的n型源极/漏极区的上部形成第一硼增强区的方法，并且第二硼增强区同时形成在上部 PMOS（p型金属氧化物半导体）器件的p型源/漏区的部分。 第一和第二硼增强区域延伸到小于或等于约10纳米的深度。

    Low-Resistance Interconnects and Methods of Making Same
    28.
    发明申请
    Low-Resistance Interconnects and Methods of Making Same 审中-公开
    低电阻互连及其制作方法

    公开(公告)号：US20160118340A1

    公开(公告)日：2016-04-28

    申请号：US14941288

    申请日：2015-11-13

    Applicant: Micron Technology, Inc.

    Inventor： Jaydeb Goswami ,  Allen McTeer

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

    CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.

    Abstract translation: 提供了用于在半导体器件中提供低电阻互连的装置和方法。 具体地，本发明的一个或多个实施例涉及将导电材料设置在沟槽中而不在导电材料和沟槽的侧壁之间设置电阻阻挡材料，使得导电材料占据沟槽的整个宽度。 例如，沟槽可以设置在由阻挡材料制成的一个或多个触点上，例如氮化钛也可以作为种子，并且导电材料可以在氮化钛的顶部生长以填充沟槽。

    Memory Cells and Methods of Forming Memory Cells
    30.
    发明申请
    Memory Cells and Methods of Forming Memory Cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US20150179936A1

    公开(公告)日：2015-06-25

    申请号：US14618936

    申请日：2015-02-10

    Applicant: Micron Technology, Inc.

    Inventor： Martin Schubert ,  Shu Qin ,  Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

    Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.

    Abstract translation: 一些实施例包括具有第一电极的存储器单元，以及在第一电极之上并直接抵靠第一电极的中间材料。 中间材料包括对应于碳和硼之一或两者的稳定物质。 存储单元还具有超过并直接抵靠中间材料的开关材料，开关材料上方的离子储存器材料以及离子储存器材料上的第二电极。 一些实施例包括形成存储器单元的方法。

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